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Message-ID: <524d152b9e9261981b0ee3aa2ff43376a26be294.camel@mediatek.com>
Date: Wed, 5 Mar 2025 16:26:55 +0000
From: Jason-JH Lin (林睿祥) <Jason-JH.Lin@...iatek.com>
To: "robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, AngeloGioacchino Del Regno
	<angelogioacchino.delregno@...labora.com>, "conor+dt@...nel.org"
	<conor+dt@...nel.org>, "mchehab@...nel.org" <mchehab@...nel.org>,
	"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
	"jassisinghbrar@...il.com" <jassisinghbrar@...il.com>
CC: "linux-media@...r.kernel.org" <linux-media@...r.kernel.org>,
	Sirius Wang (王皓昱) <Sirius.Wang@...iatek.com>,
	Moudy Ho (何宗原) <Moudy.Ho@...iatek.com>,
	Nancy Lin (林欣螢) <Nancy.Lin@...iatek.com>,
	Xiandong Wang (王先冬)
	<Xiandong.Wang@...iatek.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@...iatek.com>,
	"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"fshao@...omium.org" <fshao@...omium.org>,
	Singo Chang (張興國) <Singo.Chang@...iatek.com>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>,
	Xavier Chang (張獻文) <Xavier.Chang@...iatek.com>,
	"matthias.bgg@...il.com" <matthias.bgg@...il.com>, "treapking@...omium.org"
	<treapking@...omium.org>
Subject: Re: [PATCH v4 5/8] soc: mediatek: mtk-cmdq: Add mminfra_offset
 compatibility for DRAM address

On Tue, 2025-03-04 at 10:37 +0100, AngeloGioacchino Del Regno wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 18/02/25 06:41, Jason-JH Lin ha scritto:
> > Since GCE has been moved to mminfra in MT8196, all transactions
> > from
> > mminfra to DRAM will have their addresses adjusted by subtracting a
> > mminfra offset.
> > This information should be handled inside the CMDQ driver, allowing
> > CMDQ users to call CMDQ APIs as usual.
> > 
> > Therefore, CMDQ driver needs to use the mbox API to get the
> > mminfra_offset value of the SoC, and then add it to the DRAM
> > address
> > when generating instructions to ensure GCE accesses the correct
> > DRAM
> > address.
> > 
> > Signed-off-by: Jason-JH Lin <jason-jh.lin@...iatek.com>
> > ---
> >   drivers/soc/mediatek/mtk-cmdq-helper.c | 35
> > ++++++++++++++++++++++++--
> >   1 file changed, 33 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> > b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > index aa9853100d78..f2853a74af01 100644
> > --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> > +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > @@ -314,10 +314,22 @@ EXPORT_SYMBOL(cmdq_pkt_write_s_mask_value);
> > 
> >   int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr,
> > dma_addr_t dst_addr)
> >   {
> > +     struct cmdq_client *cl = (struct cmdq_client *)pkt->cl;
> >       const u16 high_addr_reg_idx  = CMDQ_THR_SPR_IDX0;
> >       const u16 value_reg_idx = CMDQ_THR_SPR_IDX1;
> >       int ret;
> > 
> > +     if (!cl) {
> > +             pr_err("%s %d: pkt->cl is NULL!\n", __func__,
> > __LINE__);
> > +             return -EINVAL;
> > +     }
> > +
> > +     if (cmdq_addr_need_offset(cl->chan, src_addr))
> > +             src_addr += cmdq_get_offset_pa(cl->chan);
> 
> If the offset is just DRAM IOSTART, you could manage that differently
> in the cmdq
> helper as well as the cmdq mailbox... :-)
> 

The offset_pa is not DRAM IOSTART, it is the MMINFRA subtracting
offset.

CMDQ helper is used to generate the instruction to the command buffer.
Since this offset_pa is added for the PA put into the instruction, I
think adding the offset_pa here is more suitable than CMDQ mailbox.
Does that make sense? :-)

Regards,
Jason-JH Lin

> > +
> > +     if (cmdq_addr_need_offset(cl->chan, dst_addr))
> > +             dst_addr += cmdq_get_offset_pa(cl->chan);
> > +
> Cheers,
> Angelo

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