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Message-ID: <qr5vsq5b4pf5po3uq4esrozfjkmzq5q55tqlxxc74fh2pcygzi@vb7txcm5wpst>
Date: Wed, 5 Mar 2025 04:57:50 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Melody Olvera <quic_molvera@...cinc.com>
Cc: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Wesley Cheng <quic_wcheng@...cinc.com>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Philipp Zabel <p.zabel@...gutronix.de>, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 7/9] arm64: dts: qcom: sm8750: Add USB support to
SM8750 SoCs
On Tue, Mar 04, 2025 at 01:56:40PM -0800, Melody Olvera wrote:
> From: Wesley Cheng <quic_wcheng@...cinc.com>
>
> Add the base USB devicetree definitions for SM8750 platforms. The overall
> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
> (rev. v8) and M31 eUSB2 PHY. The major difference for SM8750 is the
> transition to using the M31 eUSB2 PHY compared to previous SoCs.
>
> Enable USB support on SM8750 MTP and QRD variants. SM8750 has a QMP combo
> PHY for the SSUSB path, and a M31 eUSB2 PHY for the HSUSB path.
>
> Signed-off-by: Wesley Cheng <quic_wcheng@...cinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 163 +++++++++++++++++++++++++++++++++++
> 1 file changed, 163 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..e543e65c7aba3213ca0b8a8f6dbaf1371ed8317e 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> #include <dt-bindings/power/qcom,rpmhpd.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> @@ -1966,6 +1967,168 @@ lpass_lpicx_noc: interconnect@...0000 {
> #interconnect-cells = <2>;
> };
>
> + usb_1_hsphy: phy@...3000 {
> + compatible = "qcom,sm8750-m31-eusb2-phy";
> + reg = <0x0 0x88e3000 0x0 0x29c>;
> +
> + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + usb_dp_qmpphy: phy@...8000 {
> + compatible = "qcom,sm8750-qmp-usb3-dp-phy";
> + reg = <0x0 0x088e8000 0x0 0x4000>;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "usb3_pipe";
> +
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> + reset-names = "phy",
> + "common";
> +
> + power-domains = <&gcc GCC_USB3_PHY_GDSC>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> +
> + orientation-switch;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_dp_qmpphy_out: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_dp_qmpphy_usb_ss_in: endpoint {
> + remote-endpoint = <&usb_1_dwc3_ss>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + usb_dp_qmpphy_dp_in: endpoint {
> + };
> + };
> + };
> + };
> +
> + usb_1: usb@...8800 {
> + compatible = "qcom,sm8750-dwc3", "qcom,dwc3";
> + reg = <0x0 0x0a6f8800 0x0 0x400>;
> + status = "disabled";
Status should be the last property
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&tcsrcc TCSR_USB3_CLKREF_EN>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "xo";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
Misaligned
> + <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pwr_event",
> + "hs_phy_irq",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq",
> + "ss_phy_irq";
> +
> + power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
QCOM_ICC_TAG_ALWAYS
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
> + interconnect-names = "usb-ddr", "apps-usb";
> +
--
With best wishes
Dmitry
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