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Message-Id: <20250306021840.2120016-3-maobibo@loongson.cn>
Date: Thu, 6 Mar 2025 10:18:40 +0800
From: Bibo Mao <maobibo@...ngson.cn>
To: Tianrui Zhao <zhaotianrui@...ngson.cn>,
Huacai Chen <chenhuacai@...nel.org>
Cc: WANG Xuerui <kernel@...0n.name>,
kvm@...r.kernel.org,
loongarch@...ts.linux.dev,
linux-kernel@...r.kernel.org,
Xianglai Li <lixianglai@...ngson.cn>
Subject: [PATCH v2 2/2] LoongArch: KVM: Add interrupt checking with Loongson AVEC
There is newly added macro INT_AVEC with CSR ESTAT register, which is
bit 14 used for Loongson AVEC support. AVEC interrupt status bit 14 is
supported with macro CSR_ESTAT_IS, here replace hardcoded value 0x1fff
with macro CSR_ESTAT_IS so that AVEC interrupt status is supported by
KVM also.
Signed-off-by: Bibo Mao <maobibo@...ngson.cn>
---
arch/loongarch/kvm/vcpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c
index 20f941af3e9e..9e1a9b4aa4c6 100644
--- a/arch/loongarch/kvm/vcpu.c
+++ b/arch/loongarch/kvm/vcpu.c
@@ -311,7 +311,7 @@ static int kvm_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
{
int ret = RESUME_GUEST;
unsigned long estat = vcpu->arch.host_estat;
- u32 intr = estat & 0x1fff; /* Ignore NMI */
+ u32 intr = estat & CSR_ESTAT_IS;
u32 ecode = (estat & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
vcpu->mode = OUTSIDE_GUEST_MODE;
--
2.39.3
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