linux-kernel - Re: [PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding

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Message-ID: <CAPVz0n3EwU=N4Fr+HEKTEM-nwmYb+Lm7NHPjg7OXUH4dhnGm0A@mail.gmail.com>
Date: Fri, 7 Mar 2025 16:05:50 +0200
From: Svyatoslav Ryhel <clamor95@...il.com>
To: Thierry Reding <treding@...dia.com>
Cc: devicetree@...r.kernel.org, Svyatoslav Ryhel <clamor95@...il.com>, 
	Jonathan Hunter <jonathanh@...dia.com>, linux-tegra@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Conor Dooley <conor+dt@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding

пт, 7 бер. 2025 р. о 10:11 Svyatoslav Ryhel <clamor95@...il.com> пише:
>
> Add nodes for devices on the HOST1X bus: VI, ISP, ISPB, MSENC and TSEC.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> ---
>  arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 ++++++++++++++++++++++++++
>  1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
> index ec4f0e346b2b..8181e5d88654 100644
> --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
> @@ -103,6 +103,45 @@ host1x@...00000 {
>
>                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
>
> +               vi@...80000 {
> +                       compatible = "nvidia,tegra124-vi";
> +                       reg = <0x0 0x54080000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_VI>;
> +                       resets = <&tegra_car 20>;
> +                       reset-names = "vi";
> +
> +                       iommus = <&mc TEGRA_SWGROUP_VI>;
> +
> +                       status = "disabled";
> +               };
> +
> +               isp@...00000 {
> +                       compatible = "nvidia,tegra124-isp";
> +                       reg = <0x0 0x54600000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_ISP>;
> +                       resets = <&tegra_car TEGRA124_CLK_ISP>;
> +                       reset-names = "isp";
> +
> +                       iommus = <&mc TEGRA_SWGROUP_ISP2>;
> +
> +                       status = "disabled";
> +               };
> +
> +               isp@...80000 {
> +                       compatible = "nvidia,tegra124-isp";
> +                       reg = <0x0 0x54680000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_ISPB>;
> +                       resets = <&tegra_car TEGRA124_CLK_ISPB>;
> +                       reset-names = "ispb";

Thierry, here ispb is typo and should be just isp, obviously. I can
re-upload patchset or you may adjust it when applying. Let me know
what you would prefer.

> +
> +                       iommus = <&mc TEGRA_SWGROUP_ISP2B>;
> +
> +                       status = "disabled";
> +               };
> +
>                 dc@...00000 {
>                         compatible = "nvidia,tegra124-dc";
>                         reg = <0x0 0x54200000 0x0 0x00040000>;
> @@ -209,6 +248,32 @@ dsib: dsi@...00000 {
>                         #size-cells = <0>;
>                 };
>
> +               msenc@...c0000 {
> +                       compatible = "nvidia,tegra124-msenc";
> +                       reg = <0x0 0x544c0000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_MSENC>;
> +                       resets = <&tegra_car TEGRA124_CLK_MSENC>;
> +                       reset-names = "msenc";
> +
> +                       iommus = <&mc TEGRA_SWGROUP_MSENC>;
> +
> +                       status = "disabled";
> +               };
> +
> +               tsec@...00000 {
> +                       compatible = "nvidia,tegra124-tsec";
> +                       reg = <0x0 0x54500000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_TSEC>;
> +                       resets = <&tegra_car TEGRA124_CLK_TSEC>;
> +                       reset-names = "tsec";
> +
> +                       iommus = <&mc TEGRA_SWGROUP_TSEC>;
> +
> +                       status = "disabled";
> +               };
> +
>                 sor@...40000 {
>                         compatible = "nvidia,tegra124-sor";
>                         reg = <0x0 0x54540000 0x0 0x00040000>;
> --
> 2.43.0
>