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Message-ID: <4ac5aa09-81c2-4f12-87a7-5ac7799a8d98@oracle.com>
Date: Fri, 7 Mar 2025 11:29:27 -0800
From: ross.philipson@...cle.com
To: Jarkko Sakkinen <jarkko@...nel.org>
Cc: linux-kernel@...r.kernel.org, x86@...nel.org,
        linux-integrity@...r.kernel.org, linux-doc@...r.kernel.org,
        linux-crypto@...r.kernel.org, kexec@...ts.infradead.org,
        linux-efi@...r.kernel.org, iommu@...ts.linux-foundation.org,
        dpsmith@...rtussolutions.com, tglx@...utronix.de, mingo@...hat.com,
        bp@...en8.de, hpa@...or.com, dave.hansen@...ux.intel.com,
        ardb@...nel.org, mjg59@...f.ucam.org,
        James.Bottomley@...senpartnership.com, peterhuewe@....de, jgg@...pe.ca,
        luto@...capital.net, nivedita@...m.mit.edu,
        herbert@...dor.apana.org.au, davem@...emloft.net, corbet@....net,
        ebiederm@...ssion.com, dwmw2@...radead.org, baolu.lu@...ux.intel.com,
        kanth.ghatraju@...cle.com, andrew.cooper3@...rix.com,
        trenchboot-devel@...glegroups.com
Subject: Re: [PATCH v12 07/19] x86/msr: Add variable MTRR base/mask and x2apic
 ID registers

On 3/6/25 9:55 PM, Jarkko Sakkinen wrote:
> On Thu, Dec 19, 2024 at 11:42:04AM -0800, Ross Philipson wrote:
>> These values are needed by Secure Launch to locate particular CPUs
>> during AP startup and to restore the MTRR state after a TXT launch.
> 
> Hmm... does the first part with like locating particular CPU cores?
> 
> I'd start also the sentence with the action taken except assuring
> why the undefined action is taken.
> 
> "Add the MSR values required by Secure Launch (SL) to locate particular
> CPU cores during application processor (AP) startup, and restore the
> MTRR state after a Intel TXT launch."

Yes we can adopt something like that. Thanks for the suggestion.

Ross

> 
> Along the lines would be more informative...
> 
> BR, Jarkko


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