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Message-ID: <bec4277a-3491-448f-9d27-dd10e549ad43@oracle.com>
Date: Fri, 7 Mar 2025 11:43:00 -0800
From: ross.philipson@...cle.com
To: Jarkko Sakkinen <jarkko@...nel.org>
Cc: linux-kernel@...r.kernel.org, x86@...nel.org,
        linux-integrity@...r.kernel.org, linux-doc@...r.kernel.org,
        linux-crypto@...r.kernel.org, kexec@...ts.infradead.org,
        linux-efi@...r.kernel.org, iommu@...ts.linux-foundation.org,
        dpsmith@...rtussolutions.com, tglx@...utronix.de, mingo@...hat.com,
        bp@...en8.de, hpa@...or.com, dave.hansen@...ux.intel.com,
        ardb@...nel.org, mjg59@...f.ucam.org,
        James.Bottomley@...senpartnership.com, peterhuewe@....de, jgg@...pe.ca,
        luto@...capital.net, nivedita@...m.mit.edu,
        herbert@...dor.apana.org.au, davem@...emloft.net, corbet@....net,
        ebiederm@...ssion.com, dwmw2@...radead.org, baolu.lu@...ux.intel.com,
        kanth.ghatraju@...cle.com, andrew.cooper3@...rix.com,
        trenchboot-devel@...glegroups.com
Subject: Re: [PATCH v12 10/19] x86: Secure Launch kernel late boot stub

On 3/6/25 11:02 PM, Jarkko Sakkinen wrote:
> On Thu, Dec 19, 2024 at 11:42:07AM -0800, Ross Philipson wrote:
>> The routine slaunch_setup is called out of the x86 specific setup_arch()
>> routine during early kernel boot. After determining what platform is
>> present, various operations specific to that platform occur. This
>> includes finalizing setting for the platform late launch and verifying
>> that memory protections are in place.
>>
>> Intel VT-d/IOMMU hardware provides special registers called Protected
>> Memory Regions (PMRs) that allow all memory to be protected from
>> DMA during a TXT DRTM launch. This coverage is validated during the
> 
> Hair cutting again. Check through patch set:
> 
> 1. D-RTM
> 2. DRTM
> 
> Pick one and use it consistently. Small details like this in the end
> make the overall thing less exhausting to read.

Will do, thanks.

Ross

> 
> 
> BR, Jarkko


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