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Message-ID: <C7684E03-36E0-4D58-B6F0-78F4DB82D737@zytor.com>
Date: Thu, 06 Mar 2025 19:18:56 -0800
From: "H. Peter Anvin" <hpa@...or.com>
To: "Ahmed S. Darwish" <darwi@...utronix.de>, Borislav Petkov <bp@...en8.de>,
Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>
CC: Thomas Gleixner <tglx@...utronix.de>,
Andrew Cooper <andrew.cooper3@...rix.com>, x86@...nel.org,
John Ogness <john.ogness@...utronix.de>, x86-cpuid@...ts.linux.dev,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 10/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0
On March 6, 2025 12:49:58 PM PST, "Ahmed S. Darwish" <darwi@...utronix.de> wrote:
>Update kcpuid's CSV file to version v2.0, as generated by the
>x86-cpuid-db project.
>
>Summary of the v2.0 changes:
>
>- Introduce the leaves:
>
> - Leaf 0x00000003, Transmeta Processor serial number
> - Leaf 0x80860000, Transmeta max leaf number + CPU vendor ID
> - Leaf 0x80860001, Transmeta extended CPU information
> - Leaf 0x80860002, Transmeta Code Morphing Software (CMS) enumeration
> - Leaf 0x80860003 => 0x80860006, Transmeta CPU information string
> - Leaf 0x80860007, Transmeta "live" CPU information
> - Leaf 0xc0000000, Centaur/Zhaoxin's max leaf number
> - Leaf 0xc0000001, Centaur/Zhaoxin's extended CPU features
>
>- Add a 0x prefix for leaves 0x0 to 0x9. This maintains consistency with
> the rest of the CSV entries.
>
>- Add new bitfields:
>
> - Leaf 0x7: nmi_src, NMI-source reporting with FRED event data
> - Leaf 0x80000001: e_base_type and e_mmx (Transmeta)
>
>- Update the section headers for leaves 0x80000000 and 0x80000005 to
> indicate that they are also valid for Transmeta CPUs.
>
>Signed-off-by: Ahmed S. Darwish <darwi@...utronix.de>
>Link: https://lkml.kernel.org/r/ZwU0HtmCTj2rF2T8@lx-t490
>---
> tools/arch/x86/kcpuid/cpuid.csv | 648 +++++++++++++++++++-------------
> 1 file changed, 382 insertions(+), 266 deletions(-)
>
>diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
>index d751eb8585d0..d0f7159f99ba 100644
>--- a/tools/arch/x86/kcpuid/cpuid.csv
>+++ b/tools/arch/x86/kcpuid/cpuid.csv
>@@ -1,5 +1,5 @@
> # SPDX-License-Identifier: CC0-1.0
>-# Generator: x86-cpuid-db v1.0
>+# Generator: x86-cpuid-db v2.0
>
> #
> # Auto-generated file.
>@@ -12,297 +12,306 @@
> # Leaf 0H
> # Maximum standard leaf number + CPU vendor string
>
>- 0, 0, eax, 31:0, max_std_leaf , Highest cpuid standard leaf supported
>- 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
>- 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
>- 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
>+ 0x0, 0, eax, 31:0, max_std_leaf , Highest cpuid standard leaf supported
>+ 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
>+ 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
>+ 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
>
> # Leaf 1H
> # CPU FMS (Family/Model/Stepping) + standard feature flags
>
>- 1, 0, eax, 3:0, stepping , Stepping ID
>- 1, 0, eax, 7:4, base_model , Base CPU model ID
>- 1, 0, eax, 11:8, base_family_id , Base CPU family ID
>- 1, 0, eax, 13:12, cpu_type , CPU type
>- 1, 0, eax, 19:16, ext_model , Extended CPU model ID
>- 1, 0, eax, 27:20, ext_family , Extended CPU family ID
>- 1, 0, ebx, 7:0, brand_id , Brand index
>- 1, 0, ebx, 15:8, clflush_size , CLFLUSH instruction cache line size
>- 1, 0, ebx, 23:16, n_logical_cpu , Logical CPU (HW threads) count
>- 1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID
>- 1, 0, ecx, 0, pni , Streaming SIMD Extensions 3 (SSE3)
>- 1, 0, ecx, 1, pclmulqdq , PCLMULQDQ instruction support
>- 1, 0, ecx, 2, dtes64 , 64-bit DS save area
>- 1, 0, ecx, 3, monitor , MONITOR/MWAIT support
>- 1, 0, ecx, 4, ds_cpl , CPL Qualified Debug Store
>- 1, 0, ecx, 5, vmx , Virtual Machine Extensions
>- 1, 0, ecx, 6, smx , Safer Mode Extensions
>- 1, 0, ecx, 7, est , Enhanced Intel SpeedStep
>- 1, 0, ecx, 8, tm2 , Thermal Monitor 2
>- 1, 0, ecx, 9, ssse3 , Supplemental SSE3
>- 1, 0, ecx, 10, cid , L1 Context ID
>- 1, 0, ecx, 11, sdbg , Sillicon Debug
>- 1, 0, ecx, 12, fma , FMA extensions using YMM state
>- 1, 0, ecx, 13, cx16 , CMPXCHG16B instruction support
>- 1, 0, ecx, 14, xtpr , xTPR Update Control
>- 1, 0, ecx, 15, pdcm , Perfmon and Debug Capability
>- 1, 0, ecx, 17, pcid , Process-context identifiers
>- 1, 0, ecx, 18, dca , Direct Cache Access
>- 1, 0, ecx, 19, sse4_1 , SSE4.1
>- 1, 0, ecx, 20, sse4_2 , SSE4.2
>- 1, 0, ecx, 21, x2apic , X2APIC support
>- 1, 0, ecx, 22, movbe , MOVBE instruction support
>- 1, 0, ecx, 23, popcnt , POPCNT instruction support
>- 1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation
>- 1, 0, ecx, 25, aes , AES instructions
>- 1, 0, ecx, 26, xsave , XSAVE (and related instructions) support
>- 1, 0, ecx, 27, osxsave , XSAVE (and related instructions) are enabled by OS
>- 1, 0, ecx, 28, avx , AVX instructions support
>- 1, 0, ecx, 29, f16c , Half-precision floating-point conversion support
>- 1, 0, ecx, 30, rdrand , RDRAND instruction support
>- 1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system
>- 1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)
>- 1, 0, edx, 1, vme , Virtual-8086 Mode Extensions
>- 1, 0, edx, 2, de , Debugging Extensions
>- 1, 0, edx, 3, pse , Page Size Extension
>- 1, 0, edx, 4, tsc , Time Stamp Counter
>- 1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR support)
>- 1, 0, edx, 6, pae , Physical Address Extensions
>- 1, 0, edx, 7, mce , Machine Check Exception
>- 1, 0, edx, 8, cx8 , CMPXCHG8B instruction
>- 1, 0, edx, 9, apic , APIC on-chip
>- 1, 0, edx, 11, sep , SYSENTER, SYSEXIT, and associated MSRs
>- 1, 0, edx, 12, mtrr , Memory Type Range Registers
>- 1, 0, edx, 13, pge , Page Global Extensions
>- 1, 0, edx, 14, mca , Machine Check Architecture
>- 1, 0, edx, 15, cmov , Conditional Move Instruction
>- 1, 0, edx, 16, pat , Page Attribute Table
>- 1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
>- 1, 0, edx, 18, pn , Processor Serial Number
>- 1, 0, edx, 19, clflush , CLFLUSH instruction
>- 1, 0, edx, 21, dts , Debug Store
>- 1, 0, edx, 22, acpi , Thermal monitor and clock control
>- 1, 0, edx, 23, mmx , MMX instructions
>- 1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions
>- 1, 0, edx, 25, sse , SSE instructions
>- 1, 0, edx, 26, sse2 , SSE2 instructions
>- 1, 0, edx, 27, ss , Self Snoop
>- 1, 0, edx, 28, ht , Hyper-threading
>- 1, 0, edx, 29, tm , Thermal Monitor
>- 1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now resreved
>- 1, 0, edx, 31, pbe , Pending Break Enable
>+ 0x1, 0, eax, 3:0, stepping , Stepping ID
>+ 0x1, 0, eax, 7:4, base_model , Base CPU model ID
>+ 0x1, 0, eax, 11:8, base_family_id , Base CPU family ID
>+ 0x1, 0, eax, 13:12, cpu_type , CPU type
>+ 0x1, 0, eax, 19:16, ext_model , Extended CPU model ID
>+ 0x1, 0, eax, 27:20, ext_family , Extended CPU family ID
>+ 0x1, 0, ebx, 7:0, brand_id , Brand index
>+ 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH instruction cache line size
>+ 0x1, 0, ebx, 23:16, n_logical_cpu , Logical CPU (HW threads) count
>+ 0x1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID
>+ 0x1, 0, ecx, 0, pni , Streaming SIMD Extensions 3 (SSE3)
>+ 0x1, 0, ecx, 1, pclmulqdq , PCLMULQDQ instruction support
>+ 0x1, 0, ecx, 2, dtes64 , 64-bit DS save area
>+ 0x1, 0, ecx, 3, monitor , MONITOR/MWAIT support
>+ 0x1, 0, ecx, 4, ds_cpl , CPL Qualified Debug Store
>+ 0x1, 0, ecx, 5, vmx , Virtual Machine Extensions
>+ 0x1, 0, ecx, 6, smx , Safer Mode Extensions
>+ 0x1, 0, ecx, 7, est , Enhanced Intel SpeedStep
>+ 0x1, 0, ecx, 8, tm2 , Thermal Monitor 2
>+ 0x1, 0, ecx, 9, ssse3 , Supplemental SSE3
>+ 0x1, 0, ecx, 10, cid , L1 Context ID
>+ 0x1, 0, ecx, 11, sdbg , Sillicon Debug
>+ 0x1, 0, ecx, 12, fma , FMA extensions using YMM state
>+ 0x1, 0, ecx, 13, cx16 , CMPXCHG16B instruction support
>+ 0x1, 0, ecx, 14, xtpr , xTPR Update Control
>+ 0x1, 0, ecx, 15, pdcm , Perfmon and Debug Capability
>+ 0x1, 0, ecx, 17, pcid , Process-context identifiers
>+ 0x1, 0, ecx, 18, dca , Direct Cache Access
>+ 0x1, 0, ecx, 19, sse4_1 , SSE4.1
>+ 0x1, 0, ecx, 20, sse4_2 , SSE4.2
>+ 0x1, 0, ecx, 21, x2apic , X2APIC support
>+ 0x1, 0, ecx, 22, movbe , MOVBE instruction support
>+ 0x1, 0, ecx, 23, popcnt , POPCNT instruction support
>+ 0x1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation
>+ 0x1, 0, ecx, 25, aes , AES instructions
>+ 0x1, 0, ecx, 26, xsave , XSAVE (and related instructions) support
>+ 0x1, 0, ecx, 27, osxsave , XSAVE (and related instructions) are enabled by OS
>+ 0x1, 0, ecx, 28, avx , AVX instructions support
>+ 0x1, 0, ecx, 29, f16c , Half-precision floating-point conversion support
>+ 0x1, 0, ecx, 30, rdrand , RDRAND instruction support
>+ 0x1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system
>+ 0x1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)
>+ 0x1, 0, edx, 1, vme , Virtual-8086 Mode Extensions
>+ 0x1, 0, edx, 2, de , Debugging Extensions
>+ 0x1, 0, edx, 3, pse , Page Size Extension
>+ 0x1, 0, edx, 4, tsc , Time Stamp Counter
>+ 0x1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR support)
>+ 0x1, 0, edx, 6, pae , Physical Address Extensions
>+ 0x1, 0, edx, 7, mce , Machine Check Exception
>+ 0x1, 0, edx, 8, cx8 , CMPXCHG8B instruction
>+ 0x1, 0, edx, 9, apic , APIC on-chip
>+ 0x1, 0, edx, 11, sep , SYSENTER, SYSEXIT, and associated MSRs
>+ 0x1, 0, edx, 12, mtrr , Memory Type Range Registers
>+ 0x1, 0, edx, 13, pge , Page Global Extensions
>+ 0x1, 0, edx, 14, mca , Machine Check Architecture
>+ 0x1, 0, edx, 15, cmov , Conditional Move Instruction
>+ 0x1, 0, edx, 16, pat , Page Attribute Table
>+ 0x1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
>+ 0x1, 0, edx, 18, pn , Processor Serial Number
>+ 0x1, 0, edx, 19, clflush , CLFLUSH instruction
>+ 0x1, 0, edx, 21, dts , Debug Store
>+ 0x1, 0, edx, 22, acpi , Thermal monitor and clock control
>+ 0x1, 0, edx, 23, mmx , MMX instructions
>+ 0x1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions
>+ 0x1, 0, edx, 25, sse , SSE instructions
>+ 0x1, 0, edx, 26, sse2 , SSE2 instructions
>+ 0x1, 0, edx, 27, ss , Self Snoop
>+ 0x1, 0, edx, 28, ht , Hyper-threading
>+ 0x1, 0, edx, 29, tm , Thermal Monitor
>+ 0x1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now resreved
>+ 0x1, 0, edx, 31, pbe , Pending Break Enable
>
> # Leaf 2H
> # Intel cache and TLB information one-byte descriptors
>
>- 2, 0, eax, 7:0, iteration_count , Number of times this CPUD leaf must be queried
>- 2, 0, eax, 15:8, desc1 , Descriptor #1
>- 2, 0, eax, 23:16, desc2 , Descriptor #2
>- 2, 0, eax, 30:24, desc3 , Descriptor #3
>- 2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
>- 2, 0, ebx, 7:0, desc4 , Descriptor #4
>- 2, 0, ebx, 15:8, desc5 , Descriptor #5
>- 2, 0, ebx, 23:16, desc6 , Descriptor #6
>- 2, 0, ebx, 30:24, desc7 , Descriptor #7
>- 2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
>- 2, 0, ecx, 7:0, desc8 , Descriptor #8
>- 2, 0, ecx, 15:8, desc9 , Descriptor #9
>- 2, 0, ecx, 23:16, desc10 , Descriptor #10
>- 2, 0, ecx, 30:24, desc11 , Descriptor #11
>- 2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set
>- 2, 0, edx, 7:0, desc12 , Descriptor #12
>- 2, 0, edx, 15:8, desc13 , Descriptor #13
>- 2, 0, edx, 23:16, desc14 , Descriptor #14
>- 2, 0, edx, 30:24, desc15 , Descriptor #15
>- 2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
>+ 0x2, 0, eax, 7:0, iteration_count , Number of times this CPUD leaf must be queried
>+ 0x2, 0, eax, 15:8, desc1 , Descriptor #1
>+ 0x2, 0, eax, 23:16, desc2 , Descriptor #2
>+ 0x2, 0, eax, 30:24, desc3 , Descriptor #3
>+ 0x2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
>+ 0x2, 0, ebx, 7:0, desc4 , Descriptor #4
>+ 0x2, 0, ebx, 15:8, desc5 , Descriptor #5
>+ 0x2, 0, ebx, 23:16, desc6 , Descriptor #6
>+ 0x2, 0, ebx, 30:24, desc7 , Descriptor #7
>+ 0x2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
>+ 0x2, 0, ecx, 7:0, desc8 , Descriptor #8
>+ 0x2, 0, ecx, 15:8, desc9 , Descriptor #9
>+ 0x2, 0, ecx, 23:16, desc10 , Descriptor #10
>+ 0x2, 0, ecx, 30:24, desc11 , Descriptor #11
>+ 0x2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set
>+ 0x2, 0, edx, 7:0, desc12 , Descriptor #12
>+ 0x2, 0, edx, 15:8, desc13 , Descriptor #13
>+ 0x2, 0, edx, 23:16, desc14 , Descriptor #14
>+ 0x2, 0, edx, 30:24, desc15 , Descriptor #15
>+ 0x2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
>+
>+# Leaf 3H
>+# Transmeta Processor Serial Number (PSN)
>+
>+ 0x3, 0, eax, 31:0, cpu_psn_0 , Processor Serial Number bytes 0 - 3
>+ 0x3, 0, ebx, 31:0, cpu_psn_1 , Processor Serial Number bytes 4 - 7
>+ 0x3, 0, ecx, 31:0, cpu_psn_2 , Processor Serial Number bytes 8 - 11
>+ 0x3, 0, edx, 31:0, cpu_psn_3 , Processor Serial Number bytes 12 - 15
>
> # Leaf 4H
> # Intel deterministic cache parameters
>
>- 4, 31:0, eax, 4:0, cache_type , Cache type field
>- 4, 31:0, eax, 7:5, cache_level , Cache level (1-based)
>- 4, 31:0, eax, 8, cache_self_init , Self-initialializing cache level
>- 4, 31:0, eax, 9, fully_associative , Fully-associative cache
>- 4, 31:0, eax, 25:14, num_threads_sharing , Number logical CPUs sharing this cache
>- 4, 31:0, eax, 31:26, num_cores_on_die , Number of cores in the physical package
>- 4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
>- 4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
>- 4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
>- 4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
>- 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
>- 4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
>- 4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function)
>+ 0x4, 31:0, eax, 4:0, cache_type , Cache type field
>+ 0x4, 31:0, eax, 7:5, cache_level , Cache level (1-based)
>+ 0x4, 31:0, eax, 8, cache_self_init , Self-initialializing cache level
>+ 0x4, 31:0, eax, 9, fully_associative , Fully-associative cache
>+ 0x4, 31:0, eax, 25:14, num_threads_sharing , Number logical CPUs sharing this cache
>+ 0x4, 31:0, eax, 31:26, num_cores_on_die , Number of cores in the physical package
>+ 0x4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
>+ 0x4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
>+ 0x4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
>+ 0x4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
>+ 0x4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
>+ 0x4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
>+ 0x4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function)
>
> # Leaf 5H
> # MONITOR/MWAIT instructions enumeration
>
>- 5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes
>- 5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes
>- 5, 0, ecx, 0, mwait_ext , Enumeration of MONITOR/MWAIT extensions is supported
>- 5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is supported
>- 5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using MWAIT
>- 5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using MWAIT
>- 5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using MWAIT
>- 5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using MWAIT
>- 5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using MWAIT
>- 5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using MWAIT
>- 5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using MWAIT
>- 5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using MWAIT
>+ 0x5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes
>+ 0x5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes
>+ 0x5, 0, ecx, 0, mwait_ext , Enumeration of MONITOR/MWAIT extensions is supported
>+ 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is supported
>+ 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using MWAIT
>+ 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using MWAIT
>+ 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using MWAIT
>+ 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using MWAIT
>+ 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using MWAIT
>+ 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using MWAIT
>+ 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using MWAIT
>+ 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using MWAIT
>
> # Leaf 6H
> # Thermal and Power Management enumeration
>
>- 6, 0, eax, 0, dtherm , Digital temprature sensor
>- 6, 0, eax, 1, turbo_boost , Intel Turbo Boost
>- 6, 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-state)
>- 6, 0, eax, 4, pln , Power Limit Notification (PLN) event
>- 6, 0, eax, 5, ecmd , Clock modulation duty cycle extension
>- 6, 0, eax, 6, pts , Package thermal management
>- 6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers are supported
>- 6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR)
>- 6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported
>- 6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference
>- 6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request
>- 6, 0, eax, 13, hdc_base_regs , HDC base registers are supported
>- 6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0
>- 6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change
>- 6, 0, eax, 16, hwp_peci_override , HWP PECI override
>- 6, 0, eax, 17, hwp_flexible , Flexible HWP
>- 6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode
>- 6, 0, eax, 19, hfi , HW_FEEDBACK MSRs supported
>- 6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP req is supported
>- 6, 0, eax, 23, thread_director , Intel thread director support
>- 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 is supported
>- 6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds
>- 6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface)
>- 6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR support
>- 6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director
>- 6, 0, edx, 0, perfcap_reporting , Performance capability reporting
>- 6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
>- 6, 0, edx, 11:8, feedback_sz , HW feedback interface struct size, in 4K pages
>- 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU index @ HW feedback struct, 0-based
>+ 0x6, 0, eax, 0, dtherm , Digital temprature sensor
>+ 0x6, 0, eax, 1, turbo_boost , Intel Turbo Boost
>+ 0x6, 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-state)
>+ 0x6, 0, eax, 4, pln , Power Limit Notification (PLN) event
>+ 0x6, 0, eax, 5, ecmd , Clock modulation duty cycle extension
>+ 0x6, 0, eax, 6, pts , Package thermal management
>+ 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers are supported
>+ 0x6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR)
>+ 0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported
>+ 0x6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference
>+ 0x6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request
>+ 0x6, 0, eax, 13, hdc_base_regs , HDC base registers are supported
>+ 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0
>+ 0x6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change
>+ 0x6, 0, eax, 16, hwp_peci_override , HWP PECI override
>+ 0x6, 0, eax, 17, hwp_flexible , Flexible HWP
>+ 0x6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode
>+ 0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs supported
>+ 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP req is supported
>+ 0x6, 0, eax, 23, thread_director , Intel thread director support
>+ 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 is supported
>+ 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds
>+ 0x6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface)
>+ 0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR support
>+ 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director
>+ 0x6, 0, edx, 0, perfcap_reporting , Performance capability reporting
>+ 0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
>+ 0x6, 0, edx, 11:8, feedback_sz , HW feedback interface struct size, in 4K pages
>+ 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU index @ HW feedback struct, 0-based
>
> # Leaf 7H
> # Extended CPU features enumeration
>
>- 7, 0, eax, 31:0, leaf7_n_subleaves , Number of cpuid 0x7 subleaves
>- 7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write support
>- 7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR supported
>- 7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions)
>- 7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1
>- 7, 0, ebx, 4, hle , Hardware Lock Elision
>- 7, 0, ebx, 5, avx2 , AVX2 instruction set
>- 7, 0, ebx, 6, fdp_excptn_only , FPU Data Pointer updated only on x87 exceptions
>- 7, 0, ebx, 7, smep , Supervisor Mode Execution Protection
>- 7, 0, ebx, 8, bmi2 , Bit manipulation extensions group 2
>- 7, 0, ebx, 9, erms , Enhanced REP MOVSB/STOSB
>- 7, 0, ebx, 10, invpcid , I
Leaf 3h was not unique to Transmeta.
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