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Message-ID: <20250307034454.12243-13-guangjie.song@mediatek.com>
Date: Fri, 7 Mar 2025 11:44:36 +0800
From: Guangjie Song <guangjie.song@...iatek.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Matthias Brugger
<matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, Ulf Hansson
<ulf.hansson@...aro.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>,
<linux-pm@...r.kernel.org>, Guangjie Song <guangjie.song@...iatek.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH 12/13] dt-bindings: power: mediatek: Add new MT8196 power domain
Add the binding documentation for power domain on MediaTek MT8196.
Signed-off-by: Guangjie Song <guangjie.song@...iatek.com>
---
.../mediatek,mt8196-power-controller.yaml | 74 +++++++++++++++++++
include/dt-bindings/power/mt8196-power.h | 57 ++++++++++++++
2 files changed, 131 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/mediatek,mt8196-power-controller.yaml
create mode 100644 include/dt-bindings/power/mt8196-power.h
diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8196-power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8196-power-controller.yaml
new file mode 100644
index 000000000000..6c2867b25967
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/mediatek,mt8196-power-controller.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/mediatek,mt8196-power-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT8196 Power Domains Controller
+
+maintainers:
+ - Guangjie Song <guangjie.song@...iatek.com>
+
+description: |
+ Mediatek processors include support for multiple power domains which can be
+ powered up/down by software based on different application scenes to save power.
+
+properties:
+ $nodename:
+ pattern: '^power-controller(@[0-9a-f]+)?$'
+
+ compatible:
+ enum:
+ - mediatek,mt8196-scpsys
+ - mediatek,mt8196-hfrpsys
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ description: Address range of the power controller.
+
+ clocks:
+ description: |
+ A number of phandles to clocks that need to be enabled during domain
+ power-up sequencing.
+
+ clock-names:
+ description: |
+ List of names of clock.
+
+ domain-supply:
+ description: domain regulator supply.
+
+ spm:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the spm register range.
+
+ mmpc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the mmpc register range.
+
+ vote-regmap:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the vote register range.
+
+ mm-vote-regmap:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the mm-vote register range.
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/power/mt8196-power.h>
+
+ scpsys: power-controller@...04000 {
+ compatible = "mediatek,mt8196-scpsys", "syscon";
+ reg = <0 0x1c004000 0 0x1000>;
+ #power-domain-cells = <1>;
+ spm = <&scpsys_bus>;
+ vote-regmap = <&vote>;
+ };
diff --git a/include/dt-bindings/power/mt8196-power.h b/include/dt-bindings/power/mt8196-power.h
new file mode 100644
index 000000000000..b0db89cc435d
--- /dev/null
+++ b/include/dt-bindings/power/mt8196-power.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ * Author: Chong-ming Wei <chong-ming.wei@...iatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8196_POWER_H
+#define _DT_BINDINGS_POWER_MT8196_POWER_H
+
+/* SPM */
+#define MT8196_POWER_DOMAIN_CONN 0
+#define MT8196_POWER_DOMAIN_SSUSB_P0 1
+#define MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0 2
+#define MT8196_POWER_DOMAIN_SSUSB_P1 3
+#define MT8196_POWER_DOMAIN_SSUSB_P23 4
+#define MT8196_POWER_DOMAIN_SSUSB_PHY_P2 5
+#define MT8196_POWER_DOMAIN_PEXTP_MAC0 6
+#define MT8196_POWER_DOMAIN_PEXTP_MAC1 7
+#define MT8196_POWER_DOMAIN_PEXTP_MAC2 8
+#define MT8196_POWER_DOMAIN_PEXTP_PHY0 9
+#define MT8196_POWER_DOMAIN_PEXTP_PHY1 10
+#define MT8196_POWER_DOMAIN_PEXTP_PHY2 11
+#define MT8196_POWER_DOMAIN_ADSP_AO 12
+#define MT8196_POWER_DOMAIN_ADSP_INFRA 13
+#define MT8196_POWER_DOMAIN_AUDIO 14
+#define MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT 15
+#define MT8196_POWER_DOMAIN_MM_PROC_DORMANT 16
+#define MT8196_POWER_DOMAIN_SSR 17
+#define MT8196_SPM_POWER_DOMAIN_NR 18
+
+/* MMPC */
+#define MT8196_POWER_DOMAIN_MM_INFRA_AO 0
+#define MT8196_POWER_DOMAIN_MM_INFRA0 1
+#define MT8196_POWER_DOMAIN_MM_INFRA1 2
+#define MT8196_POWER_DOMAIN_VDE_VCORE0 3
+#define MT8196_POWER_DOMAIN_VDE0 4
+#define MT8196_POWER_DOMAIN_VDE1 5
+#define MT8196_POWER_DOMAIN_VEN0 6
+#define MT8196_POWER_DOMAIN_VEN1 7
+#define MT8196_POWER_DOMAIN_VEN2 8
+#define MT8196_POWER_DOMAIN_DISP_VCORE 9
+#define MT8196_POWER_DOMAIN_DIS0_DORMANT 10
+#define MT8196_POWER_DOMAIN_DIS1_DORMANT 11
+#define MT8196_POWER_DOMAIN_OVL0_DORMANT 12
+#define MT8196_POWER_DOMAIN_OVL1_DORMANT 13
+#define MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT 14
+#define MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT 15
+#define MT8196_POWER_DOMAIN_MML0_SHUTDOWN 16
+#define MT8196_POWER_DOMAIN_MML1_SHUTDOWN 17
+#define MT8196_POWER_DOMAIN_CSI_BS_RX 18
+#define MT8196_POWER_DOMAIN_CSI_LS_RX 19
+#define MT8196_POWER_DOMAIN_DSI_PHY0 20
+#define MT8196_POWER_DOMAIN_DSI_PHY1 21
+#define MT8196_POWER_DOMAIN_DSI_PHY2 22
+#define MT8196_MMPC_POWER_DOMAIN_NR 23
+
+#endif /* _DT_BINDINGS_POWER_MT8196_POWER_H */
--
2.45.2
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