linux-kernel - [tip: timers/vdso] vdso: Introduce vdso/cache.h

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Message-ID: <174144150586.14745.11473965032857056650.tip-bot2@tip-bot2>
Date: Sat, 08 Mar 2025 13:45:05 -0000
From:
 tip-bot2 for Thomas Weißschuh <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: thomas.weissschuh@...utronix.de, Thomas Gleixner <tglx@...utronix.de>,
 x86@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip: timers/vdso] vdso: Introduce vdso/cache.h

The following commit has been merged into the timers/vdso branch of tip:

Commit-ID:     0704bf439655c1f82ff7e623b1124a3c1cb8c907
Gitweb:        https://git.kernel.org/tip/0704bf439655c1f82ff7e623b1124a3c1cb8c907
Author:        Thomas Weißschuh <thomas.weissschuh@...utronix.de>
AuthorDate:    Mon, 03 Mar 2025 12:11:03 +01:00
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Sat, 08 Mar 2025 14:37:39 +01:00

vdso: Introduce vdso/cache.h

The vDSO implementation can only include headers from the vdso/
namespace. To enable the usage of ____cacheline_aligned from
the vDSO, move it and its dependencies into a new header vdso/cache.h.
Keep compatibility by including vdso/cache.h from linux/cache.h.

Signed-off-by: Thomas Weißschuh <thomas.weissschuh@...utronix.de>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Link: https://lore.kernel.org/all/20250303-vdso-clock-v1-1-c1b5c69a166f@linutronix.de

---
 include/linux/cache.h |  9 +--------
 include/vdso/cache.h  | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 8 deletions(-)
 create mode 100644 include/vdso/cache.h

diff --git a/include/linux/cache.h b/include/linux/cache.h
index ca2a056..e69768f 100644
--- a/include/linux/cache.h
+++ b/include/linux/cache.h
@@ -3,16 +3,13 @@
 #define __LINUX_CACHE_H
 
 #include <uapi/linux/kernel.h>
+#include <vdso/cache.h>
 #include <asm/cache.h>
 
 #ifndef L1_CACHE_ALIGN
 #define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES)
 #endif
 
-#ifndef SMP_CACHE_BYTES
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-#endif
-
 /**
  * SMP_CACHE_ALIGN - align a value to the L2 cacheline size
  * @x: value to align
@@ -63,10 +60,6 @@
 #define __ro_after_init __section(".data..ro_after_init")
 #endif
 
-#ifndef ____cacheline_aligned
-#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
-#endif
-
 #ifndef ____cacheline_aligned_in_smp
 #ifdef CONFIG_SMP
 #define ____cacheline_aligned_in_smp ____cacheline_aligned
diff --git a/include/vdso/cache.h b/include/vdso/cache.h
new file mode 100644
index 0000000..f89d483
--- /dev/null
+++ b/include/vdso/cache.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __VDSO_CACHE_H
+#define __VDSO_CACHE_H
+
+#include <asm/cache.h>
+
+#ifndef SMP_CACHE_BYTES
+#define SMP_CACHE_BYTES L1_CACHE_BYTES
+#endif
+
+#ifndef ____cacheline_aligned
+#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
+#endif
+
+#endif	/* __VDSO_ALIGN_H */