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Message-ID: <aff4fd18-59a2-4378-bfd2-840bcd1a2392@oss.qualcomm.com>
Date: Sat, 8 Mar 2025 16:08:49 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: George Moussalem <george.moussalem@...look.com>,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org,
andersson@...nel.org, bhelgaas@...gle.com, conor+dt@...nel.org,
devicetree@...r.kernel.org, dmitry.baryshkov@...aro.org,
kishon@...nel.org, konradybcio@...nel.org, krzk+dt@...nel.org,
kw@...ux.com, lpieralisi@...nel.org, manivannan.sadhasivam@...aro.org,
p.zabel@...gutronix.de, quic_nsekar@...cinc.com, robh@...nel.org,
robimarko@...il.com, vkoul@...nel.org
Cc: quic_srichara@...cinc.com
Subject: Re: [PATCH v3 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes
On 5.03.2025 2:41 PM, George Moussalem wrote:
> From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>
> From: Nitheesh Sekar <quic_nsekar@...cinc.com>
>
> Add phy and controller nodes for a 2-lane Gen2 and
> a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> one global interrupt.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@...cinc.com>
> Signed-off-by: Sricharan R <quic_srichara@...cinc.com>
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
> ---
[...]
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
Please all the comments in this patch, they're not very useful
Konrad
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