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Message-ID: <87ecz422ea.ffs@tglx>
Date: Mon, 10 Mar 2025 18:58:53 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Neil Armstrong
<neil.armstrong@...aro.org>, Kevin Hilman <khilman@...libre.com>, Jerome
Brunet <jbrunet@...libre.com>, Martin Blumenstingl
<martin.blumenstingl@...glemail.com>, Heiner Kallweit
<hkallweit1@...il.com>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-amlogic@...ts.infradead.org,
Xianwei Zhao <xianwei.zhao@...ogic.com>
Subject: Re: [PATCH v4 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
On Fri, Mar 07 2025 at 16:49, Xianwei Zhao via wrote:
>
> if (type == IRQ_TYPE_EDGE_BOTH) {
> val |= BIT(ctl->params->edge_both_offset + idx);
Not new, but this really should be 'val = ...'
> - meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
> + meson_gpio_irq_update_bits(ctl, params->edge_pol_reg,
> BIT(ctl->params->edge_both_offset + idx), val);
and this BIT() calculation is obviously redundant as it is the same as @val.
Would be nice to have that cleaned up.
With that fixed:
Reviewed-by: Thomas Gleixner <tglx@...utronix.de>
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