linux-kernel - [PATCH v4 6/8] arm64: dts: qcom: qcs8300: enable pcie0 interface

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Message-Id: <20250310063103.3924525-7-quic_ziyuzhan@quicinc.com>
Date: Mon, 10 Mar 2025 14:31:01 +0800
From: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
To: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
        manivannan.sadhasivam@...aro.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, vkoul@...nel.org, kishon@...nel.org,
        andersson@...nel.org, konradybcio@...nel.org,
        dmitry.baryshkov@...aro.org, neil.armstrong@...aro.org,
        abel.vesa@...aro.org
Cc: quic_ziyuzhan@...cinc.com, quic_qianyu@...cinc.com,
        quic_krichai@...cinc.com, johan+linaro@...nel.org,
        linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-phy@...ts.infradead.org,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH v4 6/8] arm64: dts: qcom: qcs8300: enable pcie0 interface

Add configurations in devicetree for PCIe0, board related gpios,
PMIC regulators, etc.

Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 40 +++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index b5c9f89b3435..c3fe3b98b1b6 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -285,6 +285,23 @@ queue3 {
 	};
 };
 
+&pcie0 {
+	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie0_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l6a>;
+	vdda-pll-supply = <&vreg_l5a>;
+
+	status = "okay";
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -310,6 +327,29 @@ &serdes0 {
 };
 
 &tlmm {
+	pcie0_default_state: pcie0-default-state {
+		wake-pins {
+			pins = "gpio0";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		clkreq-pins {
+			pins = "gpio1";
+			function = "pcie0_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-pins {
+			pins = "gpio2";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
 	ethernet0_default: ethernet0-default-state {
 		ethernet0_mdc: ethernet0-mdc-pins {
 			pins = "gpio5";
-- 
2.34.1