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Message-ID: <20250311142825.2727171-1-liujianfeng1994@gmail.com>
Date: Tue, 11 Mar 2025 22:27:50 +0800
From: Jianfeng Liu <liujianfeng1994@...il.com>
To: linux-rockchip@...ts.infradead.org
Cc: Jianfeng Liu <liujianfeng1994@...il.com>,
Conor Dooley <conor+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Rob Herring <robh@...nel.org>,
Stephen Rothwell <sfr@...b.auug.org.au>,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] arm64: dts: rockchip: Add AP6275P wireless support to ArmSoM Sige7
ArmSoM Sige7 uses the PCI-e AP6275P Wi-Fi 6 module. The pcie@0 node can
be used as Bridge1, so the wifi@0 node is used as a device under the
Bridege 1 similar with Khadas Edge 2.
Signed-off-by: Jianfeng Liu <liujianfeng1994@...il.com>
---
.../boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
index 6a0fffaa26ee..face42bb0d7d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
@@ -300,6 +300,22 @@ &pcie2x1l0 {
&pcie2x1l1 {
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x300000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x30 0x3f>;
+
+ wifi: wifi@0,0 {
+ compatible = "pci14e4,449d";
+ reg = <0x310000 0 0 0 0>;
+ clocks = <&hym8563>;
+ clock-names = "lpo";
+ };
+ };
};
/* phy0 - left ethernet port */
--
2.43.0
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