linux-kernel - Re: [PATCH v3 6/7] riscv: add a data fence for CMODX in the kernel mode

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Message-ID: <87ldtbwrdb.fsf@all.your.base.are.belong.to.us>
Date: Tue, 11 Mar 2025 15:53:36 +0100
From: Björn Töpel <bjorn@...nel.org>
To: Andrea Parri <parri.andrea@...il.com>
Cc: Andy Chiu <andybnac@...il.com>, Paul Walmsley
 <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
 <aou@...s.berkeley.edu>, linux-riscv@...ts.infradead.org,
 linux-kernel@...r.kernel.org, bjorn@...osinc.com, puranjay12@...il.com,
 alexghiti@...osinc.com, yongxuan.wang@...ive.com, greentime.hu@...ive.com,
 nick.hu@...ive.com, nylon.chen@...ive.com, tommy.wu@...ive.com,
 eric.lin@...ive.com, viccent.chen@...ive.com, zong.li@...ive.com,
 samuel.holland@...ive.com
Subject: Re: [PATCH v3 6/7] riscv: add a data fence for CMODX in the kernel
 mode

Andrea Parri <parri.andrea@...il.com> writes:

>> FWIW, the for S-IMSIC the write is already writel(), so we'll have the
>> text patching and IPI ordered. Regardless, there's more than one flavor
>> of IPI on RISC-V!
>
> AFAIU, this writel() is intended to order the insertion (and the initialization)
> of the CSD object before the MMIO writes; so, the "right fix" seems to turn the
> "other flavors" into using a writel() or providing a similar ordering guarantee.

Yes, that's probably the right approach, or maybe follow-up!

> As a bonus, such change should address/fix all current and future occurrences of
> the message-passing scenario in question (the patch addressed the occurrence in
> flush_icache_all(), but there appears to be a similar one in flush_icache_mm()).

Indeed. I wonder if the SBI remote fence.i needs it?


Cheers,
Björn