linux-kernel - Re: [PATCH 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible

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Message-ID: <20250311-sedate-dazzling-1d17139aa6aa@spud>
Date: Tue, 11 Mar 2025 18:14:33 +0000
From: Conor Dooley <conor@...nel.org>
To: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Samuel Holland <samuel.holland@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Min Lin <linmin@...incomputing.com>,
	Pritesh Patel <pritesh.patel@...fochips.com>,
	Yangyu Chen <cyy@...self.name>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	Yu Chien Peter Lin <peterlin@...estech.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	Kanak Shilledar <kanakshilledar@...il.com>,
	Darshan Prajapati <darshan.prajapati@...fochips.com>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	Heiko Stuebner <heiko@...ech.de>, Aradhya Bhatia <a-bhatia1@...com>,
	rafal@...ecki.pl, Anup Patel <anup@...infault.org>,
	devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible

On Tue, Mar 11, 2025 at 01:04:23PM +0530, Pinkesh Vaghela wrote:
> From: Darshan Prajapati <darshan.prajapati@...fochips.com>
> 
> Update Documentation for supporting SiFive P550 based CPU
> 
> Signed-off-by: Darshan Prajapati <darshan.prajapati@...fochips.com>
> Reviewed-by: Samuel Holland <samuel.holland@...ive.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 2c72f148a74b..3ee7468001f6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -51,6 +51,7 @@ properties:
>                - sifive,e5
>                - sifive,e7
>                - sifive,e71
> +              - sifive,p550
>                - sifive,rocket0
>                - sifive,s7
>                - sifive,u5
> -- 
> 2.25.1
> 

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