linux-kernel - [PATCH 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20250311073432.4068512-2-pinkesh.vaghela@einfochips.com>
Date: Tue, 11 Mar 2025 13:04:23 +0530
From: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
To: Conor Dooley <conor@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
	Samuel Holland <samuel.holland@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Min Lin <linmin@...incomputing.com>,
	Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>,
	Pritesh Patel <pritesh.patel@...fochips.com>,
	Yangyu Chen <cyy@...self.name>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	Yu Chien Peter Lin <peterlin@...estech.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	Kanak Shilledar <kanakshilledar@...il.com>,
	Darshan Prajapati <darshan.prajapati@...fochips.com>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	Heiko Stuebner <heiko@...ech.de>,
	Aradhya Bhatia <a-bhatia1@...com>,
	rafal@...ecki.pl,
	Anup Patel <anup@...infault.org>,
	devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible

From: Darshan Prajapati <darshan.prajapati@...fochips.com>

Update Documentation for supporting SiFive P550 based CPU

Signed-off-by: Darshan Prajapati <darshan.prajapati@...fochips.com>
Reviewed-by: Samuel Holland <samuel.holland@...ive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 2c72f148a74b..3ee7468001f6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -51,6 +51,7 @@ properties:
               - sifive,e5
               - sifive,e7
               - sifive,e71
+              - sifive,p550
               - sifive,rocket0
               - sifive,s7
               - sifive,u5
-- 
2.25.1