linux-kernel - Re: [PATCH v2 1/8] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain

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Message-ID: <e0f534c8-5a86-448f-a164-f5d691484721@quicinc.com>
Date: Tue, 11 Mar 2025 14:17:24 +0530
From: Jagadeesh Kona <quic_jkona@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>,
        Ajit Pandey
	<quic_ajipan@...cinc.com>,
        Imran Shaik <quic_imrashai@...cinc.com>,
        "Taniya
 Das" <quic_tdas@...cinc.com>,
        Satya Priya Kakitapalli
	<quic_skakitap@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Subject: Re: [PATCH v2 1/8] dt-bindings: clock: qcom,sm8450-videocc: Add MXC
 power domain



On 3/6/2025 3:40 PM, Dmitry Baryshkov wrote:
> On Thu, Mar 06, 2025 at 02:25:33PM +0530, Jagadeesh Kona wrote:
>> To configure the video PLLs and enable the video GDSCs on SM8450,
>> SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along
>> with MMCX. Therefore, update the videocc bindings to include
>> the MXC power domain on these platforms.
>>
>> Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller")
>> Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
>> Acked-by: Rob Herring (Arm) <robh@...nel.org>
>> ---
>>  Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++---
>>  1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> @@ -32,9 +32,11 @@ properties:
>>        - description: Video AHB clock from GCC
>>  
>>    power-domains:
>> -    maxItems: 1
>>      description:
>> -      MMCX power domain.
>> +      Power domains required for the clock controller to operate
>> +    items:
>> +      - description: MMCX power domain
>> +      - description: MXC power domain
>>  
>>    required-opps:
>>      maxItems: 1
>> @@ -72,7 +74,8 @@ examples:
>>        reg = <0x0aaf0000 0x10000>;
>>        clocks = <&rpmhcc RPMH_CXO_CLK>,
>>                 <&gcc GCC_VIDEO_AHB_CLK>;
>> -      power-domains = <&rpmhpd RPMHPD_MMCX>;
>> +      power-domains = <&rpmhpd RPMHPD_MMCX>,
>> +                      <&rpmhpd RPMHPD_MXC>;
>>        required-opps = <&rpmhpd_opp_low_svs>;
> 
> As pointed out by Vladimir, you probably also need a second entry in
> required-opps.
> 

Sure, will check and add second entry in the required-opps.

Thanks,
Jagadeesh

>>        #clock-cells = <1>;
>>        #reset-cells = <1>;
>>
>> -- 
>> 2.34.1
>>
>