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Message-Id: <174169362764.507381.11220476979416149386.b4-ty@kernel.org>
Date: Tue, 11 Mar 2025 12:47:07 +0100
From: Vinod Koul <vkoul@...nel.org>
To: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
manivannan.sadhasivam@...aro.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, kishon@...nel.org, andersson@...nel.org,
konradybcio@...nel.org, dmitry.baryshkov@...aro.org,
neil.armstrong@...aro.org, abel.vesa@...aro.org,
Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Cc: quic_qianyu@...cinc.com, quic_krichai@...cinc.com,
johan+linaro@...nel.org, linux-arm-msm@...r.kernel.org,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org
Subject: Re: (subset) [PATCH v4 0/8] pci: qcom: Add QCS8300 PCIe support
On Mon, 10 Mar 2025 14:30:55 +0800, Ziyue Zhang wrote:
> This series adds document, phy, configs support for PCIe in QCS8300.
> The series depend on the following devicetree.
>
> PCIe SMMU:
> https://lore.kernel.org/all/20250206-qcs8300-pcie-smmu-v1-1-8eee0e3585bc@quicinc.com/
>
> Have follwing changes:
> - Document the QMP PCIe PHY on the QCS8300 platform.
> - Add dedicated schema for the PCIe controllers found on QCS8300.
> - Add compatible for qcs8300 platform.
> - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
> - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
>
> [...]
Applied, thanks!
[1/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2
commit: e46e59b77a9e6f322ef1ad08a8874211f389cf47
[2/8] phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300
commit: ebf198f17b5ac967db6256f4083bbcbdcc2a3100
Best regards,
--
~Vinod
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