lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <202503121721.1nslvluh-lkp@intel.com>
Date: Wed, 12 Mar 2025 17:49:02 +0800
From: kernel test robot <lkp@...el.com>
To: David Kaplan <david.kaplan@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Borislav Petkov <bp@...en8.de>,
	Josh Poimboeuf <jpoimboe@...nel.org>,
	Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
	Ingo Molnar <mingo@...hat.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
	"H . Peter Anvin" <hpa@...or.com>
Cc: llvm@...ts.linux.dev, oe-kbuild-all@...ts.linux.dev,
	linux-kernel@...r.kernel.org, Brendan Jackman <jackmanb@...gle.com>,
	Derek Manwaring <derekmn@...zon.com>
Subject: Re: [PATCH v4 11/36] x86/bugs: Restructure spectre_v2_user mitigation

Hi David,

kernel test robot noticed the following build warnings:

[auto build test WARNING on tip/master]
[cannot apply to tip/x86/core linus/master tip/auto-latest tip/smp/core v6.14-rc6 next-20250311]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/David-Kaplan/x86-bugs-Restructure-mds-mitigation/20250311-005151
base:   tip/master
patch link:    https://lore.kernel.org/r/20250310164023.779191-12-david.kaplan%40amd.com
patch subject: [PATCH v4 11/36] x86/bugs: Restructure spectre_v2_user mitigation
config: x86_64-allnoconfig (https://download.01.org/0day-ci/archive/20250312/202503121721.1nslvluh-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250312/202503121721.1nslvluh-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503121721.1nslvluh-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> arch/x86/kernel/cpu/bugs.c:1490:7: warning: variable 'smt_possible' set but not used [-Wunused-but-set-variable]
    1490 |         bool smt_possible = IS_ENABLED(CONFIG_SMP);
         |              ^
   1 warning generated.


vim +/smt_possible +1490 arch/x86/kernel/cpu/bugs.c

  1487	
  1488	static void __init spectre_v2_user_update_mitigation(void)
  1489	{
> 1490		bool smt_possible = IS_ENABLED(CONFIG_SMP);
  1491	
  1492		if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
  1493			return;
  1494	
  1495		if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
  1496		    cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
  1497			smt_possible = false;
  1498	
  1499		/* The spectre_v2 cmd line can override spectre_v2_user options */
  1500		if (spectre_v2_cmd == SPECTRE_V2_CMD_NONE) {
  1501			spectre_v2_user_ibpb = SPECTRE_V2_USER_NONE;
  1502			spectre_v2_user_stibp = SPECTRE_V2_USER_NONE;
  1503		} else if (spectre_v2_cmd == SPECTRE_V2_CMD_FORCE) {
  1504			spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
  1505			spectre_v2_user_stibp = SPECTRE_V2_USER_STRICT;
  1506		}
  1507	
  1508		/*
  1509		 * If no STIBP, Intel enhanced IBRS is enabled, or SMT impossible, STIBP
  1510		 * is not required.
  1511		 *
  1512		 * Intel's Enhanced IBRS also protects against cross-thread branch target
  1513		 * injection in user-mode as the IBRS bit remains always set which
  1514		 * implicitly enables cross-thread protections.  However, in legacy IBRS
  1515		 * mode, the IBRS bit is set only on kernel entry and cleared on return
  1516		 * to userspace.  AMD Automatic IBRS also does not protect userspace.
  1517		 * These modes therefore disable the implicit cross-thread protection,
  1518		 * so allow for STIBP to be selected in those cases.
  1519		 */
  1520		if (!boot_cpu_has(X86_FEATURE_STIBP) ||
  1521		    !cpu_smt_possible() ||
  1522		    (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
  1523		     !boot_cpu_has(X86_FEATURE_AUTOIBRS))) {
  1524			spectre_v2_user_stibp = SPECTRE_V2_USER_NONE;
  1525			return;
  1526		}
  1527	
  1528		if (spectre_v2_user_stibp != SPECTRE_V2_USER_NONE &&
  1529		    (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
  1530		     retbleed_mitigation == RETBLEED_MITIGATION_IBPB)) {
  1531			if (spectre_v2_user_stibp != SPECTRE_V2_USER_STRICT &&
  1532			    spectre_v2_user_stibp != SPECTRE_V2_USER_STRICT_PREFERRED)
  1533				pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
  1534			spectre_v2_user_stibp = SPECTRE_V2_USER_STRICT_PREFERRED;
  1535		}
  1536		pr_info("%s\n", spectre_v2_user_strings[spectre_v2_user_stibp]);
  1537	}
  1538	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ