linux-kernel - Re: [PATCH v8 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors

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Message-ID: <4f4e317d-58b2-4059-b112-3c1b78318bbe@zohomail.com>
Date: Thu, 13 Mar 2025 09:03:48 +0800
From: Li Ming <ming.li@...omail.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>
Cc: Ard Biesheuvel <ardb@...nel.org>,
 Alison Schofield <alison.schofield@...el.com>,
 Vishal Verma <vishal.l.verma@...el.com>, Ira Weiny <ira.weiny@...el.com>,
 Dan Williams <dan.j.williams@...el.com>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>,
 Yazen Ghannam <yazen.ghannam@....com>, Terry Bowman <terry.bowman@....com>,
 linux-efi@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-cxl@...r.kernel.org
Subject: Re: [PATCH v8 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS
 errors

On 3/11/2025 6:38 AM, Smita Koralahalli wrote:
> The CXL drivers use kernel trace functions for logging endpoint and
> Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality
> is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL
> Upstream Switch Ports.
>
> Introduce trace logging functions for both RAS correctable and
> uncorrectable errors specific to CXL PCIe Ports. Use them to trace
> FW-First Protocol errors.
>
> Co-developed-by: Terry Bowman <terry.bowman@....com>
> Signed-off-by: Terry Bowman <terry.bowman@....com>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>
> Reviewed-by: Ira Weiny <ira.weiny@...el.com>

Reviewed-by: Li Ming <ming.li@...omail.com>