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Message-ID: <CAKddAkBwkVQS7UtVvXCdLxEz6bz1=_X1u1CGUPm-OHiyAD4Dsw@mail.gmail.com>
Date: Thu, 13 Mar 2025 15:58:05 +0800
From: Nick Hu <nick.hu@...ive.com>
To: Conor Dooley <conor@...nel.org>
Cc: Rob Herring <robh@...nel.org>, Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
Samuel Holland <samuel.holland@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Anup Patel <anup@...infault.org>, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH] dt-bindings: timer: Add SiFive CLINT2
Hi Rob and Conor
Thanks to all your feedback.
On Wed, Mar 12, 2025 at 4:46 AM Conor Dooley <conor@...nel.org> wrote:
>
> On Tue, Mar 11, 2025 at 02:59:53PM -0500, Rob Herring wrote:
> > On Tue, Mar 11, 2025 at 01:19:03PM +0800, Nick Hu wrote:
> > > Add compatible string and property for the SiFive CLINT v2.
> > >
> > > Signed-off-by: Nick Hu <nick.hu@...ive.com>
> > > Reviewed-by: Samuel Holland <samuel.holland@...ive.com>
> > > ---
> > > .../bindings/timer/sifive,clint.yaml | 19 +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > index 76d83aea4e2b..93d74c504b5f 100644
> > > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > @@ -36,6 +36,9 @@ properties:
> > > - starfive,jh7110-clint # StarFive JH7110
> > > - starfive,jh8100-clint # StarFive JH8100
> > > - const: sifive,clint0 # SiFive CLINT v0 IP block
> >
> > Notice that we don't allow clint0 by itself. We shouldn't start now.
> >
> > > + - items:
> >
> > If you don't have a specific one yet, then add '- {}' for the first
> > entry.
> >
Do you suggest something like the following?
- items:
- {}
- const: sifive,clint2 # SiFive CLINT v2 IP block
description: SiFive CLINT v2 is the HRT that supports the Zicntr
> > > + - const: sifive,clint2 # SiFive CLINT v2 IP block
> > > + description: SiFive CLINT v2 is the HRT that supports the Zicntr
> > > - items:
> > > - enum:
> > > - allwinner,sun20i-d1-clint
> > > @@ -62,6 +65,22 @@ properties:
> > > minItems: 1
> > > maxItems: 4095
> > >
> > > + sifive,fine-ctr-bits:
> > > + description: The width in bits of the fine counter.
> >
> > maximum: 15
> >
> > Unless you know of a different maximum in which case why aren't you
> > documenting that too?
>
You are right. It's my bad. The maximum width should always be 15 in
sifive,clint2.
I should update to:
sifive,fine-ctr-bits:
maximum: 15
description: The width in bits of the fine counter.
if:
not:
properties:
compatible:
contains:
const: sifive,clint2
then:
properties:
sifive,fine-ctr-bits: false
> I'm curious why this is not something that can be discerned from the
> compatible. It's max 15, but are there actually versions of this with a
> less-than-15-bit width?
>
The width may be various on different platforms so it is possible to
have a less-than-15-bit width.
> >
> > > +
> > > +if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: sifive,clint2
> > > +then:
> > > + properties:
> > > + sifive,fine-ctr-bits:
> > > + maximum: 15
> > > +else:
> > > + properties:
> > > + sifive,fine-ctr-bits: false
> > > +
> > > additionalProperties: false
> > >
> > > required:
> > > --
> > > 2.17.1
> > >
Best Regards,
Nick
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