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Message-Id: <20250314-rzn1d400-eb-v3-1-45c4fd3f6e01@bootlin.com>
Date: Fri, 14 Mar 2025 19:56:29 +0100
From: Thomas Bonnefille <thomas.bonnefille@...tlin.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Miquèl Raynal <miquel.raynal@...tlin.com>,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Clément Léger <clement.leger@...tlin.com>,
Thomas Bonnefille <thomas.bonnefille@...tlin.com>
Subject: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board
device-tree
From: Clément Léger <clement.leger@...tlin.com>
The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
It adds support for the 2 additional switch ports (port C and D) that are
available on that board.
Signed-off-by: Clément Léger <clement.leger@...tlin.com>
[Thomas moved the dts to the renesas directory and declared the leds in
each phy]
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@...tlin.com>
---
This short series adds support for the RZ/N1 Expansion Board. This board
is a carrier board on which a daughter board (either RZ/N1D or RZ/N1S)
can be plugged. The device-tree that is added by this series enables the
use to the 2 external switch ports that are present on this board.
---
V3:
- Drop bindings commit as it was applied to master
- Move Makefile modification to arch/arm/boot/dts/renesas/Makefile
- Declare LEDs in PHY.
- Use the driver default LED configuration as there was no reason to
use a different one.
V2:
- Add "renesas,rzn1d400-db" in list of compatibles for EB board
- Replace '_' with '-' in eth pins node name
- Split some long lines in dts
---
arch/arm/boot/dts/renesas/Makefile | 1 +
.../arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts | 120 +++++++++++++++++++++
2 files changed, 121 insertions(+)
diff --git a/arch/arm/boot/dts/renesas/Makefile b/arch/arm/boot/dts/renesas/Makefile
index 833a02447ecf7a02bd2efe70fae15213ede9a6de..947c7fe0280337a3aa6e9a0257f406694892239c 100644
--- a/arch/arm/boot/dts/renesas/Makefile
+++ b/arch/arm/boot/dts/renesas/Makefile
@@ -30,4 +30,5 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
r9a06g032-rzn1d400-db.dtb \
+ r9a06g032-rzn1d400-eb.dtb \
sh73a0-kzm9g.dtb
diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
new file mode 100644
index 0000000000000000000000000000000000000000..20478941170bade197afb5cc9b3d694bd9a30951
--- /dev/null
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-EB Board
+ *
+ * Copyright (C) 2023 Schneider-Electric
+ *
+ */
+
+#include "r9a06g032-rzn1d400-db.dts"
+
+/ {
+ model = "RZN1D-EB Board";
+ compatible = "renesas,rzn1d400-eb", "renesas,rzn1d400-db",
+ "renesas,r9a06g032";
+};
+
+&mii_conv2 {
+ renesas,miic-input = <MIIC_SWITCH_PORTD>;
+ status = "okay";
+};
+
+&mii_conv3 {
+ renesas,miic-input = <MIIC_SWITCH_PORTC>;
+ status = "okay";
+};
+
+&pinctrl{
+ pins_eth1: pins-eth1 {
+ pinmux = <RZN1_PINMUX(12, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(13, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(14, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(15, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(16, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(17, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(18, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(19, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(20, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(21, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(22, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(23, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ pins_eth2: pins-eth2 {
+ pinmux = <RZN1_PINMUX(24, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(25, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(26, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(27, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(28, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(29, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(30, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(31, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(32, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(33, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(34, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(35, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
+ drive-strength = <6>;
+ bias-disable;
+ };
+};
+
+&switch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>,
+ <&pins_mdio1>;
+
+ mdio {
+ /* CN15 and CN16 switches must be configured in MDIO2 mode */
+ switch0phy1: ethernet-phy@1 {
+ reg = <1>;
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ };
+ led@1 {
+ reg = <1>;
+ };
+ led@2 {
+ reg = <2>;
+ };
+ };
+ };
+
+ switch0phy10: ethernet-phy@10 {
+ reg = <10>;
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ };
+ led@1 {
+ reg = <1>;
+ };
+ led@2 {
+ reg = <2>;
+ };
+ };
+ };
+ };
+};
+
+&switch_port2 {
+ label = "lan2";
+ phy-mode = "rgmii-id";
+ phy-handle = <&switch0phy10>;
+ status = "okay";
+};
+
+&switch_port3 {
+ label = "lan3";
+ phy-mode = "rgmii-id";
+ phy-handle = <&switch0phy1>;
+ status = "okay";
+};
---
base-commit: 9c5968db9e625019a0ee5226c7eebef5519d366a
change-id: 20250127-rzn1d400-eb-3fc1479a13e6
Best regards,
--
Thomas Bonnefille <thomas.bonnefille@...tlin.com>
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