[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <174198247887.1604753.1605423266163412383.b4-ty@kernel.org>
Date: Fri, 14 Mar 2025 15:01:03 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach <mike.leach@...aro.org>,
James Clark <james.clark@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Jie Gan <quic_jiegan@...cinc.com>
Cc: Tingwei Zhang <quic_tingweiz@...cinc.com>,
Jinlong Mao <quic_jinlmao@...cinc.com>,
coresight@...ts.linaro.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
linux-arm-msm@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com
Subject: Re: (subset) [PATCH v15 00/10] Coresight: Add Coresight TMC Control Unit driver
On Mon, 03 Mar 2025 11:29:21 +0800, Jie Gan wrote:
> From: Jie Gan <jie.gan@....qualcomm.com>
>
> The Coresight TMC Control Unit(CTCU) device hosts miscellaneous configuration
> registers to control various features related to TMC ETR device.
>
> The CTCU device works as a helper device physically connected to the TMC ETR device.
> ---------------------------------------------------------
> |ETR0| |ETR1|
> . \ / .
> . \ / .
> . \ / .
> . \ / .
> ---------------------------------------------------
> ETR0ATID0-ETR0ATID3 CTCU ETR1ATID0-ETR1ATID3
> ---------------------------------------------------
> Each ETR has four ATID registers with 128 bits long in total.
> e.g. ETR0ATID0-ETR0ATID3 registers are used by ETR0 device.
>
> [...]
Applied, thanks!
[10/10] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
commit: 05ed68070d7a061f62f502d07f883c05dc666990
Best regards,
--
Bjorn Andersson <andersson@...nel.org>
Powered by blists - more mailing lists