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Message-ID: <CACRpkda-VjHnd9q1gijWZZ0zygUogPtN6VY-G+GEqdj-EbOv9w@mail.gmail.com>
Date: Fri, 14 Mar 2025 11:05:24 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Prathamesh Shete <pshete@...dia.com>
Cc: thierry.reding@...il.com, jonathanh@...dia.com, linux-gpio@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] pinctrl: tegra: Set SFIO mode to Mux Register
On Thu, Mar 6, 2025 at 6:06 AM Prathamesh Shete <pshete@...dia.com> wrote:
> Tegra devices have an 'sfsel' bit field that determines whether a pin
> operates in SFIO (Special Function I/O) or GPIO mode. Currently,
> tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO.
>
> However, tegra_pinctrl_set_mux() can be called independently in certain
> code paths where gpio_disable_free() is not invoked. In such cases, failing
> to set the SFIO mode could lead to incorrect pin configurations, resulting
> in functional issues for peripherals relying on SFIO.
>
> This patch ensures that whenever set_mux() is called, the SFIO mode is
> correctly set in the Mux Register if the 'sfsel' bit is present. This
> prevents situations where the pin remains in GPIO mode despite being
> configured for SFIO use.
>
> Fixes: 59b67585e242 ("pinctrl: add a driver for NVIDIA Tegra")
> Signed-off-by: Prathamesh Shete <pshete@...dia.com>
Patch applied.
I can't tell how urgent this patch is so I have applied it for next
for the moment.
Yours,
Linus Walleij
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