Message-ID: <Z9hAUs1wPOIAo2nt@debian-BULLSEYE-live-builder-AMD64>
Date: Mon, 17 Mar 2025 12:31:30 -0300
From: Marcelo Schmitt <marcelo.schmitt1@...il.com>
To: Jonathan Cameron <jic23@...nel.org>
Cc: Marcelo Schmitt <marcelo.schmitt@...log.com>, linux-iio@...r.kernel.org,
	linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
	lars@...afoo.de, Michael.Hennerich@...log.com, corbet@....net
Subject: Re: [PATCH v1 1/4] iio: adc: ad4000: Add support for SPI offload

...
> > diff --git a/drivers/iio/adc/ad4000.c b/drivers/iio/adc/ad4000.c
> > index 4fe8dee48da9..6c9b71e7a2fb 100644
> > --- a/drivers/iio/adc/ad4000.c
> > +++ b/drivers/iio/adc/ad4000.c
> 
> > +
> > +static int ad4000_offload_buffer_postdisable(struct iio_dev *indio_dev)
> > +{
> > +	struct ad4000_state *st = iio_priv(indio_dev);
> > +
> > +	spi_offload_trigger_disable(st->offload, st->offload_trigger);
> 
> Trivial. Prefer a blank line before a 'simple return' like this one.
> 
Ack

> > +	return 0;
> > +}
> 
> 
...
> > +/*
> > + * This executes a data sample transfer when using SPI offloading for when the
> > + * device connections are in "3-wire" mode, selected when the adi,sdi-pin device
> > + * tree property is set to "high". In this connection mode, the ADC SDI pin is
> > + * connected to VIO and ADC CNV pin is connected to a SPI controller CS (it
> > + * can't be connected to a GPIO).
> > + *
> > + * In order to achieve the maximum sample rate, we only do one transfer per
> > + * SPI offload trigger. This has the effect that the first sample data is not
> > + * valid because it is reading the previous conversion result. We also use
> 
> Say what happens to that invalid sample.  Is it dropped or provided to userspace
> as if it were valid?  (I hope dropped!)

TL;DR: The invalid sample goes into the buffer as a valid one.

In AD4000 '3-wire' mode, data capture has a latency (delay) of one sample.

The ADC begins sampling data N at CNV rising edge
          |   +-- CNV (usually SPI CS) is brought low to begin reading the data
          |   |                                +-- Data N + 1 that will be read
          |   |                                |   on the next transfer starts 
          v   v                                v   being sampled at end of transfer N.
           ___                                  ____            
CNV  _____/   \________________________________/    \_____
                    _     _             _
SCLK ______________/ \___/ \_ ...   ___/ \_______________
                   ___   ___           ___
SDO  _____________/___\_/___\ ...   __/___\_______________
                    ^
                    |
             Data from conversion N is output from here on

A better drawing can be found in datasheet page 29, Figure 57.
https://www.analog.com/media/en/technical-documentation/data-sheets/ADAQ4003.pdf

In sum, we're always reading a conversion that started at the end of the
previous SPI transfer or, in other words, the data comes out with a latency
(delay) of one read.

Datasheet somehow mentions that by saying
	When turbo mode is enabled, the conversion result read on SDO corresponds to
	the result of the previous conversion.

I think I can do a dummy SPI transfer on buffer preenable so at least the
first data is not invalid. Would that be better?

> 
> > + * bits_per_word to ensure the minimum of SCLK cycles are used. And a delay is
> > + * added to make sure we meet the minimum quiet time before releasing the CS
> > + * line. Plus the CS change delay is set to ensure that we meet the minimum
> > + * conversion time before asserting CS again.
> > + *
> > + * This timing is only valid if turbo mode is disabled (reading during acquisition).
> > + */
> > +static int ad4000_prepare_offload_message(struct ad4000_state *st,
> > +					  const struct iio_chan_spec *chan)
> > +
> 
...
> > +		xfers[1].bits_per_word = chan->scan_type.realbits;
> >  	xfers[1].delay.value = st->time_spec->t_quiet2_ns;
> >  	xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS;
> >  
> > @@ -719,7 +1007,9 @@ static int ad4000_prepare_4wire_mode_message(struct ad4000_state *st,
> >  	xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
> >  
> >  	xfers[1].rx_buf = &st->scan.data;
> > -	xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits);
> > +	xfers[1].len = chan->scan_type.realbits > 16 ? 4 : 2;
> > +	if (chan->scan_type.endianness != IIO_BE)
> 
> This is odd enough to require a comment.  Why is endianness relevant?

When using SPI offloading (at least with PULSAR-ADC HDL project [1]), ADC data
is read by SPI controller and pushed to DMA memory in CPU endianness. I don't
know exactly where data gets rearranged in the data path (whether SPI-Engine,
the DMA controller, or something else rearranges ADC data into CPU endianess).
But I know, from testing with these ADCs and HDL project, that data is correct
when read in CPU endianness because it converts back to expected mV values.
When IIO buffers were set to IIO_BE and SPI offloading is used, data just looked
weird and didn't convert to expected values in mV.

[1]: https://analogdevicesinc.github.io/hdl/projects/pulsar_adc/index.html

Other IIO drivers also set IIO_CPU buffer endianness when using offload support,
e.g. ad7944, ad7380.

They only say buffer would use 32 storagebits when using SPI offload.
https://lore.kernel.org/linux-iio/20250207-dlech-mainline-spi-engine-offload-2-v8-10-e48a489be48c@baylibre.com/
https://lore.kernel.org/linux-iio/20250220-wip-bl-spi-offload-ad7380-v1-1-838aa873e62a@baylibre.com/#t

I also didn't expect to find out HDL support for 16-bit data width was removed.
We used to have a build parameter for 16-bit precision ADCs.
https://github.com/analogdevicesinc/hdl/commit/b2dc91b30dae891b6319d88e083f26e726f43ba0#diff-1117c2618353232e5f22aa6a12e8ae976757fa897b3425f470a12123cae26535L13

Would something like 'because SPI offloading leads to data being pushed to
memory in CPU endianness' be a reasonable comment?

...
> 
> > +		if (st->using_offload) {
> > +			indio_dev->channels = &chip->reg_access_offload_chan_spec;
> Set num_channels here
Ack for all these

> > +			ret = ad4000_prepare_offload_turbo_message(st, indio_dev->channels);
...
> 
> Also set size here.  Obviously this means a little duplication but still good
> to keep them together.
Okay, sounds reasonable.

> 
> 
> > +		}
> 
> >  	case AD4000_SDI_GND:
> > @@ -830,7 +1175,10 @@ static int ad4000_probe(struct spi_device *spi)
> >  	}
> >  
> >  	indio_dev->name = chip->dev_name;
> > -	indio_dev->num_channels = 2;
> > +	if (st->using_offload)
> > +		indio_dev->num_channels = 1;
> > +	else
> > +		indio_dev->num_channels = 2;
> 
> Move this up to where you set channels so that the array
> and size are set together.
Acknowledged as all the above cases.

Thanks,
Marcelo

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