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Message-ID: <20250317173355.157536-1-simeddon@gmail.com>
Date: Mon, 17 Mar 2025 22:55:03 +0530
From: Siddharth Menon <simeddon@...il.com>
To: linux-iio@...r.kernel.org,
lars@...afoo.de,
Michael.Hennerich@...log.com,
jic23@...nel.org,
gregkh@...uxfoundation.org
Cc: linux-kernel@...r.kernel.org,
linux-staging@...ts.linux.dev,
Siddharth Menon <simeddon@...il.com>,
Marcelo Schmitt <marcelo.schmitt1@...il.com>
Subject: [PATCH v2] iio: frequency: ad9832: Use FIELD_PREP macro to set bit fields
Refactor code to use the FIELD_PREP macro for setting bit fields
instead of manual bit manipulation.
Suggested-by: Marcelo Schmitt <marcelo.schmitt1@...il.com>
Signed-off-by: Siddharth Menon <simeddon@...il.com>
---
Based on feedback from Jonathan and Marcello, I have made the following
changes
v1->v2:
- removed CMD_SHIFT andADD_SHIFT completely
- use GENMASK
- store regval into an array and iterate through it
drivers/staging/iio/frequency/ad9832.c | 53 ++++++++++++++------------
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c
index 140ee4f9c137..0c1816505495 100644
--- a/drivers/staging/iio/frequency/ad9832.c
+++ b/drivers/staging/iio/frequency/ad9832.c
@@ -16,6 +16,8 @@
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/sysfs.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
@@ -65,11 +67,12 @@
#define AD9832_SLEEP BIT(13)
#define AD9832_RESET BIT(12)
#define AD9832_CLR BIT(11)
-#define CMD_SHIFT 12
-#define ADD_SHIFT 8
#define AD9832_FREQ_BITS 32
#define AD9832_PHASE_BITS 12
#define RES_MASK(bits) ((1 << (bits)) - 1)
+#define CMD_MASK_2 GENMASK(15, 12)
+#define ADD_MASK_2 GENMASK(11, 8)
+#define DATA_MASK_2 GENMASK(7, 0)
/**
* struct ad9832_state - driver instance specific data
@@ -131,6 +134,7 @@ static int ad9832_write_frequency(struct ad9832_state *st,
{
unsigned long clk_freq;
unsigned long regval;
+ u8 regval_bytes[4];
clk_freq = clk_get_rate(st->mclk);
@@ -138,19 +142,14 @@ static int ad9832_write_frequency(struct ad9832_state *st,
return -EINVAL;
regval = ad9832_calc_freqreg(clk_freq, fout);
+ put_unaligned_be32(regval, regval_bytes);
- st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
- (addr << ADD_SHIFT) |
- ((regval >> 24) & 0xFF));
- st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
- ((addr - 1) << ADD_SHIFT) |
- ((regval >> 16) & 0xFF));
- st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
- ((addr - 2) << ADD_SHIFT) |
- ((regval >> 8) & 0xFF));
- st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
- ((addr - 3) << ADD_SHIFT) |
- ((regval >> 0) & 0xFF));
+ for (int i = 0; i < 4; i++) {
+ st->freq_data[i] = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK,
+ (i % 2 == 0) ? AD9832_CMD_FRE8BITSW : AD9832_CMD_FRE16BITSW) |
+ FIELD_PREP(AD9832_ADD_MSK, addr - i) |
+ FIELD_PREP(AD9832_DAT_MSK, regval_bytes[i]));
+ }
return spi_sync(st->spi, &st->freq_msg);
}
@@ -158,15 +157,19 @@ static int ad9832_write_frequency(struct ad9832_state *st,
static int ad9832_write_phase(struct ad9832_state *st,
unsigned long addr, unsigned long phase)
{
+ u8 phase_bytes[2];
+
if (phase >= BIT(AD9832_PHASE_BITS))
return -EINVAL;
- st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
- (addr << ADD_SHIFT) |
- ((phase >> 8) & 0xFF));
- st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
- ((addr - 1) << ADD_SHIFT) |
- (phase & 0xFF));
+ put_unaligned_be16(phase, phase_bytes);
+
+ for (int i = 0; i < 2; i++) {
+ st->phase_data[i] = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK,
+ (i % 2 == 0) ? AD9832_CMD_PHA8BITSW : AD9832_CMD_PHA16BITSW) |
+ FIELD_PREP(AD9832_ADD_MSK, addr - i) |
+ FIELD_PREP(AD9832_DAT_MSK, phase_bytes[i]));
+ }
return spi_sync(st->spi, &st->phase_msg);
}
@@ -201,7 +204,7 @@ static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
st->ctrl_ss &= ~AD9832_SELSRC;
else
st->ctrl_ss |= AD9832_SELSRC;
- st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
+ st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SYNCSELSRC) |
st->ctrl_ss);
ret = spi_sync(st->spi, &st->msg);
break;
@@ -214,7 +217,7 @@ static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
ret = -EINVAL;
break;
}
- st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
+ st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT) |
st->ctrl_fp);
ret = spi_sync(st->spi, &st->msg);
break;
@@ -227,7 +230,7 @@ static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
st->ctrl_fp &= ~AD9832_PHASE(3);
st->ctrl_fp |= AD9832_PHASE(val);
- st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
+ st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT) |
st->ctrl_fp);
ret = spi_sync(st->spi, &st->msg);
break;
@@ -238,7 +241,7 @@ static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
else
st->ctrl_src |= AD9832_RESET;
- st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
+ st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESCLR) |
st->ctrl_src);
ret = spi_sync(st->spi, &st->msg);
break;
@@ -396,7 +399,7 @@ static int ad9832_probe(struct spi_device *spi)
spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
- st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
+ st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESCLR) |
st->ctrl_src);
ret = spi_sync(st->spi, &st->msg);
if (ret) {
--
2.48.1
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