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Message-ID: <cd3d2404-2fbd-4775-a970-b43ba8eacc27@gmail.com>
Date: Mon, 17 Mar 2025 10:33:36 +0200
From: Matti Vaittinen <mazziesaccount@...il.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Matti Vaittinen <matti.vaittinen@...rohmeurope.com>,
Jonathan Cameron <jic23@...nel.org>, Lars-Peter Clausen <lars@...afoo.de>,
Nuno Sa <nuno.sa@...log.com>, David Lechner <dlechner@...libre.com>,
Javier Carrasco <javier.carrasco.cruz@...il.com>,
Olivier Moysan <olivier.moysan@...s.st.com>,
Guillaume Stols <gstols@...libre.com>,
Dumitru Ceclan <mitrutzceclan@...il.com>,
Trevor Gamblin <tgamblin@...libre.com>,
Matteo Martelli <matteomartelli3@...il.com>,
Alisa-Dariana Roman <alisadariana@...il.com>,
João Paulo Gonçalves <joao.goncalves@...adex.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
linux-kernel@...r.kernel.org, linux-iio@...r.kernel.org
Subject: Re: [PATCH v7 06/10] iio: adc: Support ROHM BD79124 ADC
On 17/03/2025 09:57, Andy Shevchenko wrote:
> On Mon, Mar 17, 2025 at 09:07:30AM +0200, Matti Vaittinen wrote:
>> On 14/03/2025 16:37, Andy Shevchenko wrote:
>>> On Fri, Mar 14, 2025 at 11:22:37AM +0200, Matti Vaittinen wrote:
>
> ...
>
>>> Okay, it seems I misinterpreted the values you have in regmap configuration,
>>> I was under the impression that regmap is 16-bit data, but it is about address.
>>>
>>> So, we need to know why the heck HW has sparse registers
>>
>> We don't know. And we really don't even need to know it. We can just use
>> this device knowing there are some.
>
> Don't you have a channel to ask HW engineers about this?
Let's just say that ROHM is, while not huge, still rather large company.
I'm located far away from the HQ, I speak different language and I am
from very different cultural background. So, while there are some
channels, it is not always easy, clever of possible to ask (not to
mention getting answers to) "why this way" - questions :)
>>> for what is supposed
>>> to be sequential. This needs a good comment.
>>
>> I think it is quite usual that devices contain undocumented registers. Not
>> sure having a comment that this device also has some, adds much of value? I
>> suppose I can add a comment that we can't use bulk_write because registers
>> aren't in subsequent addresses - but having just removed bunch of
>> unnecessary comments from the code (as requested), I'm not sure adding this
>> one really improves situation... When one sees separate reads/writes for
>> data spread to multiple registers, he is likely to assume addresses aren't
>> subsequent.
>
> From HW design perspective it's silly to sparse hi and lo part of
> the semantically same entity. So, either the (undocumented) register
> is also part of the soup, or the registers have different semantics.
Or, the designer has not thought how software would be doing the reads.
Or, this design has originated from a design done for a very specific
purpose, which, we don't know of.
> This what needs to be commented in my opinion.
Yours,
-- Matti
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