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Message-Id: <20250320164622.6971-2-matthew.gerlach@altera.com>
Date: Thu, 20 Mar 2025 09:46:19 -0700
From: Matthew Gerlach <matthew.gerlach@...era.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
dinguyen@...nel.org,
bp@...en8.de,
tony.luck@...el.com,
james.morse@....com,
mchehab@...nel.org,
rric@...nel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-edac@...r.kernel.org
Cc: Matthew Gerlach <matthew.gerlach@...era.com>
Subject: [PATCH 1/4] dt-bindings: edac: altera-s10: Convert to YAML
Convert the device tree bindings for the Altera Stratix10 SoCFPGA ECC
Manager from text to yaml. The hardware for the device tree subnodes
have not changed since Arria10; so don't change the compatible strings
to include "-s10-".
Signed-off-by: Matthew Gerlach <matthew.gerlach@...era.com>
---
.../edac/altr,socfpga-s10-ecc-manager.yaml | 228 ++++++++++++++++++
.../bindings/edac/socfpga-eccmgr.txt | 150 ------------
MAINTAINERS | 5 +
3 files changed, 233 insertions(+), 150 deletions(-)
create mode 100644 Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
new file mode 100644
index 000000000000..ad057a63e88b
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
@@ -0,0 +1,228 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2025 Altera Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/altr,socfpga-s10-ecc-manager.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Stratix10 SoCFPGA ECC Manager (ARM64)
+
+maintainers:
+ - Matthew Gerlach <matthew.gerlach@...era.com
+
+description: |
+ The Stratix10 implementation of the SoCFPGA ECC Manager counts and corrects
+ single bit errors. Double bit errors are treated as SErrors in ARM64. This
+ implementation requires access to registers only available to the Secure
+ Device Manager (SDM) via Secure Monitor Calls (SMC).
+
+properties:
+
+ compatible:
+ items:
+ - const: altr,socfpga-s10-ecc-manager
+
+ altr,sysmgr-syscon:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ ranges: true
+
+ sdramedac:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ const: altr,sdram-edac-s10
+ altr,sdr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to SDRAM parent
+ interrupts:
+ maxItems: 1
+ required:
+ - compatible
+ - altr,sdr-syscon
+ - interrupts
+
+ ocram-ecc@...cc000:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ items:
+ - const: altr,socfpga-a10-ocram-ecc
+
+ reg:
+ maxItems: 1
+ altr,ecc-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to OCRAM parent
+ interrupts:
+ maxItems: 1
+ required:
+ - compatible
+ - reg
+ - altr,ecc-parent
+ - interrupts
+
+ usb0-ecc@...c4000:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ items:
+ - const: altr,socfpga-usb-ecc
+ reg:
+ maxItems: 1
+ altr,ecc-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to USB parent
+ interrupts:
+ maxItems: 1
+ required:
+ - compatible
+ - reg
+ - altr,ecc-parent
+ - interrupts
+
+ emac0-rx-ecc@...c0000:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ items:
+ - const: altr,socfpga-eth-mac-ecc
+ reg:
+ maxItems: 1
+ altr,ecc-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to ethernet parent
+ interrupts:
+ maxItems: 1
+ required:
+ - compatible
+ - reg
+ - altr,ecc-parent
+ - interrupts
+
+ emac0-tx-ecc@...c0400:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ items:
+ - const: altr,socfpga-eth-mac-ecc
+ reg:
+ maxItems: 1
+ altr,ecc-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to ethernet parent
+ interrupts:
+ maxItems: 1
+ required:
+ - compatible
+ - reg
+ - altr,ecc-parent
+ - interrupts
+
+ sdmmca-ecc@...c8c00:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ items:
+ - const: altr,socfpga-sdmmc-ecc
+ reg:
+ maxItems: 1
+ altr,ecc-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to ethernet parent
+ interrupts:
+ maxItems: 2
+ required:
+ - compatible
+ - reg
+ - altr,ecc-parent
+ - interrupts
+
+required:
+ - compatible
+ - altr,sysmgr-syscon
+ - "#address-cells"
+ - "#size-cells"
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ eccmgr {
+ compatible = "altr,socfpga-s10-ecc-manager";
+ altr,sysmgr-syscon = <&sysmgr>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges;
+
+ sdramedac {
+ compatible = "altr,sdram-edac-s10";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ocram-ecc@...cc000 {
+ compatible = "altr,socfpga-a10-ocram-ecc";
+ reg = <0xff8cc000 0x100>;
+ altr,ecc-parent = <&ocram>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usb0-ecc@...c4000 {
+ compatible = "altr,socfpga-usb-ecc";
+ reg = <0xff8c4000 0x100>;
+ altr,ecc-parent = <&usb0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emac0-rx-ecc@...c0000 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0000 0x100>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emac0-tx-ecc@...c0400 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0400 0x100>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sdmmca-ecc@...c8c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c8c00 0x100>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
index 8f52206cfd2a..4a1714f96bab 100644
--- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
@@ -231,153 +231,3 @@ Example:
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
-
-Stratix10 SoCFPGA ECC Manager (ARM64)
-The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
-in a shared register similar to the Arria10. However, Stratix10 ECC
-requires access to registers that can only be read from Secure Monitor
-with SMC calls. Therefore the device tree is slightly different. Note
-that only 1 interrupt is sent in Stratix10 because the double bit errors
-are treated as SErrors in ARM64 instead of IRQs in ARM32.
-
-Required Properties:
-- compatible : Should be "altr,socfpga-s10-ecc-manager"
-- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
- containing the ECC manager registers.
-- interrupts : Should be single bit error interrupt.
-- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
-- #interrupt-cells : must be set to 2.
-- #address-cells: must be 1
-- #size-cells: must be 1
-- ranges : standard definition, should translate from local addresses
-
-Subcomponents:
-
-SDRAM ECC
-Required Properties:
-- compatible : Should be "altr,sdram-edac-s10"
-- interrupts : Should be single bit error interrupt.
-
-On-Chip RAM ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-s10-ocram-ecc"
-- reg : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent OCRAM node.
-- interrupts : Should be single bit error interrupt.
-
-Ethernet FIFO ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
-- reg : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent Ethernet node.
-- interrupts : Should be single bit error interrupt.
-
-NAND FIFO ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-s10-nand-ecc"
-- reg : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent NAND node.
-- interrupts : Should be single bit error interrupt.
-
-DMA FIFO ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-s10-dma-ecc"
-- reg : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent DMA node.
-- interrupts : Should be single bit error interrupt.
-
-USB FIFO ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-s10-usb-ecc"
-- reg : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent USB node.
-- interrupts : Should be single bit error interrupt.
-
-SDMMC FIFO ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
-- reg : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent SD/MMC node.
-- interrupts : Should be single bit error interrupt for port A
- and then single bit error interrupt for port B.
-
-Example:
-
- eccmgr {
- compatible = "altr,socfpga-s10-ecc-manager";
- altr,sysmgr-syscon = <&sysmgr>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupts = <0 15 4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ranges;
-
- sdramedac {
- compatible = "altr,sdram-edac-s10";
- interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- ocram-ecc@...cc000 {
- compatible = "altr,socfpga-s10-ocram-ecc";
- reg = <ff8cc000 0x100>;
- altr,ecc-parent = <&ocram>;
- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- emac0-rx-ecc@...c0000 {
- compatible = "altr,socfpga-s10-eth-mac-ecc";
- reg = <0xff8c0000 0x100>;
- altr,ecc-parent = <&gmac0>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- emac0-tx-ecc@...c0400 {
- compatible = "altr,socfpga-s10-eth-mac-ecc";
- reg = <0xff8c0400 0x100>;
- altr,ecc-parent = <&gmac0>;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
- };
-
- nand-buf-ecc@...c8000 {
- compatible = "altr,socfpga-s10-nand-ecc";
- reg = <0xff8c8000 0x100>;
- altr,ecc-parent = <&nand>;
- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- nand-rd-ecc@...c8400 {
- compatible = "altr,socfpga-s10-nand-ecc";
- reg = <0xff8c8400 0x100>;
- altr,ecc-parent = <&nand>;
- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- nand-wr-ecc@...c8800 {
- compatible = "altr,socfpga-s10-nand-ecc";
- reg = <0xff8c8800 0x100>;
- altr,ecc-parent = <&nand>;
- interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- dma-ecc@...c9000 {
- compatible = "altr,socfpga-s10-dma-ecc";
- reg = <0xff8c9000 0x100>;
- altr,ecc-parent = <&pdma>;
- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
-
- usb0-ecc@...c4000 {
- compatible = "altr,socfpga-s10-usb-ecc";
- reg = <0xff8c4000 0x100>;
- altr,ecc-parent = <&usb0>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sdmmc-ecc@...c8c00 {
- compatible = "altr,socfpga-s10-sdmmc-ecc";
- reg = <0xff8c8c00 0x100>;
- altr,ecc-parent = <&mmc>;
- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
- <15 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c8fb060072b..236e23174719 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3191,6 +3191,11 @@ M: Dinh Nguyen <dinguyen@...nel.org>
S: Maintained
F: drivers/clk/socfpga/
+ARM/SOCFPGA EDAC BINDINGS
+M: Matthew Gerlach <matthew.gerlach@...era.com>
+S: Maintained
+F: Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
+
ARM/SOCFPGA EDAC SUPPORT
M: Dinh Nguyen <dinguyen@...nel.org>
S: Maintained
--
2.35.3
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