linux-kernel - Re: [PATCH RFC NOT TESTED 0/2] PCI: artpec6: Try to clean up artpec6_pcie_cpu_addr

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Message-ID: <20250320215405.GA1102700@bhelgaas>
Date: Thu, 20 Mar 2025 16:54:05 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Niklas Cassel <cassel@...nel.org>,
	Jesper Nilsson <jesper.nilsson@...s.com>
Cc: Frank Li <Frank.Li@....com>, Lars Persson <lars.persson@...s.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kw@...ux.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>, linux-arm-kernel@...s.com,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org
Subject: Re: [PATCH RFC NOT TESTED 0/2] PCI: artpec6: Try to clean up
 artpec6_pcie_cpu_addr_fixup()

On Tue, Mar 18, 2025 at 10:01:48AM +0100, Niklas Cassel wrote:
> On Mon, Mar 17, 2025 at 12:54:19PM -0500, Bjorn Helgaas wrote:
> > On Mon, Mar 10, 2025 at 05:47:03PM +0100, Jesper Nilsson wrote:
> > > I've now tested this patch-set together with your v9 on-top of the
> > > next-branch of the pci tree, and seems to be working good on my
> > > ARTPEC-6 set as RC:
> > > 
> > > # lspci
> > > 00:00.0 PCI bridge: Renesas Technology Corp. Device 0024
> > > 01:00.0 PCI bridge: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch (rev 05)
> > > 02:01.0 PCI bridge: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch (rev 05)
> > > 02:02.0 PCI bridge: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch (rev 05)
> > > 03:00.0 Non-Volatile memory controller: Phison Electronics Corporation E18 PCIe4 NVMe Controller (rev 01)
> > > 
> > > However, when running as EP, I found that the DT setup for pcie_ep
> > > wasn't correct:
> > > 
> > > diff --git a/arch/arm/boot/dts/axis/artpec6.dtsi b/arch/arm/boot/dts/axis/artpec6.dtsi
> > > index 399e87f72865..6d52f60d402d 100644
> > > --- a/arch/arm/boot/dts/axis/artpec6.dtsi
> > > +++ b/arch/arm/boot/dts/axis/artpec6.dtsi
> > > @@ -195,8 +195,8 @@ pcie: pcie@...50000 {
> > >  
> > >                 pcie_ep: pcie_ep@...50000 {
> > >                         compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
> > > -                       reg = <0xf8050000 0x2000
> > > -                              0xf8051000 0x2000
> > > +                       reg = <0xf8050000 0x1000
> > > +                              0xf8051000 0x1000
> > >                                0xf8040000 0x1000
> > >                                0x00000000 0x20000000>;
> > >                         reg-names = "dbi", "dbi2", "phy", "addr_space";
> > > 
> > > Even with this fix, I get a panic in dw_pcie_read_dbi() in EP-setup,
> > > both with and without:
> 
> Your fix looks correct to me.
> 
> You should even be able keep dbi as 0x2000, and simply remove the dbi2
> from "reg" and "reg-names", as the driver should be able to infer dbi2
> automatically:
> https://github.com/torvalds/linux/blob/v6.14-rc7/drivers/pci/controller/dwc/pcie-designware.c#L119-L128
> 
> But your fix seems more correct.
> You should probably also change the size of "dbi" to 0x1000 in the RC node.

Just a ping to see if there's any chance of getting this into v6.15?

To do that, I think we'd need to confirm that:

  - the endpoint issue is fixed

  - artpec6 is only used in-house

  - the DTBs are either already OK or OK after [PATCH 1/2]

  - everybody in-house is OK with updating to the new DTB.

I haven't seen anything about the endpoint part, and haven't seen
confirmation of the others.

Bjorn