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Message-ID: <86frj8m4be.wl-maz@kernel.org>
Date: Thu, 20 Mar 2025 09:36:37 +0000
From: Marc Zyngier <maz@...nel.org>
To: Peter Chen <peter.chen@...tech.com>
Cc: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
catalin.marinas@....com,
will@...nel.org,
arnd@...db.de,
linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
cix-kernel-upstream@...tech.com,
marcin@...zkiewicz.com.pl,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Fugang Duan <fugang.duan@...tech.com>
Subject: Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support
On Wed, 05 Mar 2025 05:38:22 +0000,
Peter Chen <peter.chen@...tech.com> wrote:
>
> + pmu-a520 {
> + compatible = "arm,cortex-a520-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
> + };
> +
> + pmu-a720 {
> + compatible = "arm,cortex-a720-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
> + };
> +
> + pmu-spe {
> + compatible = "arm,statistical-profiling-extension-v1";
> + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
> + };
SPE should follow the same model as the PMU, as each CPU has its own
SPE implementation, exposing different micro-architectural details.
The rest looks OK.
M.
--
Without deviation from the norm, progress is not possible.
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