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Message-ID:
<SA3PR04MB893164FCD6C4CB8924FC8DE583D82@SA3PR04MB8931.namprd04.prod.outlook.com>
Date: Thu, 20 Mar 2025 10:39:52 +0000
From: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
To: Conor Dooley <conor@...nel.org>
CC: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>, Paul Walmsley
<paul.walmsley@...ive.com>, Samuel Holland <samuel.holland@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>, Min Lin
<linmin@...incomputing.com>, Pritesh Patel <pritesh.patel@...fochips.com>,
Yangyu Chen <cyy@...self.name>, Lad Prabhakar
<prabhakar.mahadev-lad.rj@...renesas.com>, Yu Chien Peter Lin
<peterlin@...estech.com>, Charlie Jenkins <charlie@...osinc.com>, Kanak
Shilledar <kanakshilledar@...il.com>, Darshan Prajapati
<darshan.prajapati@...fochips.com>, Neil Armstrong
<neil.armstrong@...aro.org>, Heiko Stuebner <heiko@...ech.de>, Aradhya Bhatia
<a-bhatia1@...com>, "rafal@...ecki.pl" <rafal@...ecki.pl>, Anup Patel
<anup@...infault.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "linux-riscv@...ts.infradead.org"
<linux-riscv@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 00/10] Basic device tree support for ESWIN EIC7700 RISC-V
SoC
Hi Conor,
On Tue, Mar 11, 2025 at 11:38 PM, Conor Dooley wrote:
> On Tue, Mar 11, 2025 at 01:04:22PM +0530, Pinkesh Vaghela wrote:
> > Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
> > P550 CPU cluster and the first development board that uses it, the
> > SiFive HiFive Premier P550.
> >
> > This patch series adds initial device tree and also adds ESWIN
> > architecture support.
> >
> > Boot-tested using intiramfs with Linux 6.14.0-rc2 on HiFive Premier
> > P550 board using U-Boot 2024.01 and OpenSBI 1.4.
>
> There's no git tree in your MAINTAINERS entry, nor mention here of what the
> story is going to be in terms of sending patches to Arnd. Who is going to be
> doing that?
We are not currently set up for sending signed pull requests,
so for now we plan to send changes to Arnd as separate patches.
Regards,
Pinkesh
>
> Cheers,
> Conor.
>
> > Darshan Prajapati (3):
> > dt-bindings: riscv: Add SiFive P550 CPU compatible
> > dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC
> > dt-bindings: timer: Add ESWIN EIC7700 CLINT
> >
> > Min Lin (2):
> > riscv: dts: add initial support for EIC7700 SoC
> > riscv: dts: eswin: add HiFive Premier P550 board device tree
> >
> > Pinkesh Vaghela (2):
> > riscv: Add Kconfig option for ESWIN platforms
> > cache: sifive_ccache: Add ESWIN EIC7700 support
> >
> > Pritesh Patel (3):
> > dt-bindings: vendor-prefixes: add eswin
> > dt-bindings: riscv: Add SiFive HiFive Premier P550 board
> > dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC
> > compatibility
> >
> > .../bindings/cache/sifive,ccache0.yaml | 28 +-
> > .../sifive,plic-1.0.0.yaml | 1 +
> > .../devicetree/bindings/riscv/cpus.yaml | 1 +
> > .../devicetree/bindings/riscv/eswin.yaml | 29 ++
> > .../bindings/timer/sifive,clint.yaml | 1 +
> > .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> > MAINTAINERS | 7 +
> > arch/riscv/Kconfig.socs | 6 +
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/eswin/Makefile | 2 +
> > .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 ++
> > arch/riscv/boot/dts/eswin/eic7700.dtsi | 344 ++++++++++++++++++
> > drivers/cache/sifive_ccache.c | 2 +
> > 13 files changed, 450 insertions(+), 3 deletions(-) create mode
> > 100644 Documentation/devicetree/bindings/riscv/eswin.yaml
> > create mode 100644 arch/riscv/boot/dts/eswin/Makefile
> > create mode 100644
> > arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi
> >
> > --
> > 2.25.1
> >
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