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Message-Id: <20250320105449.2094192-6-pinkesh.vaghela@einfochips.com>
Date: Thu, 20 Mar 2025 16:24:44 +0530
From: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
To: Conor Dooley <conor@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Samuel Holland <samuel.holland@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Min Lin <linmin@...incomputing.com>,
Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>,
Pritesh Patel <pritesh.patel@...fochips.com>,
Yangyu Chen <cyy@...self.name>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Yu Chien Peter Lin <peterlin@...estech.com>,
Charlie Jenkins <charlie@...osinc.com>,
Kanak Shilledar <kanakshilledar@...il.com>,
Darshan Prajapati <darshan.prajapati@...fochips.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Heiko Stuebner <heiko@...ech.de>,
Aradhya Bhatia <a-bhatia1@...com>,
rafal@...ecki.pl,
Anup Patel <anup@...infault.org>,
devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v2 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
From: Pritesh Patel <pritesh.patel@...fochips.com>
This cache controller is also used on the ESWIN EIC7700 SoC.
However, it have 256KB private L2 Cache and shared L3 Cache of 4MB.
So add dedicated compatible string for it.
Signed-off-by: Pritesh Patel <pritesh.patel@...fochips.com>
Reviewed-by: Samuel Holland <samuel.holland@...ive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
---
.../bindings/cache/sifive,ccache0.yaml | 44 +++++++++++++++++--
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 7e8cebe21584..579bacb66f34 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -39,6 +39,7 @@ properties:
- const: cache
- items:
- enum:
+ - eswin,eic7700-l3-cache
- starfive,jh7100-ccache
- starfive,jh7110-ccache
- const: sifive,ccache0
@@ -55,10 +56,10 @@ properties:
enum: [2, 3]
cache-sets:
- enum: [1024, 2048]
+ enum: [1024, 2048, 4096]
cache-size:
- const: 2097152
+ enum: [2097152, 4194304]
cache-unified: true
@@ -89,6 +90,7 @@ allOf:
compatible:
contains:
enum:
+ - eswin,eic7700-l3-cache
- sifive,fu740-c000-ccache
- starfive,jh7100-ccache
- starfive,jh7110-ccache
@@ -108,6 +110,22 @@ allOf:
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: eswin,eic7700-l3-cache
+
+ then:
+ properties:
+ cache-size:
+ const: 4194304
+
+ else:
+ properties:
+ cache-size:
+ const: 2097152
+
- if:
properties:
compatible:
@@ -122,11 +140,31 @@ allOf:
cache-sets:
const: 2048
- else:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,mpfs-ccache
+ - sifive,fu540-c000-ccache
+
+ then:
properties:
cache-sets:
const: 1024
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - eswin,eic7700-l3-cache
+
+ then:
+ properties:
+ cache-sets:
+ const: 4096
+
- if:
properties:
compatible:
--
2.25.1
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