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Message-ID: <CAPVz0n3tY8sTvWD-QPA+_FJWnwbSeHXLJYTrk1pJzpy1enMexg@mail.gmail.com>
Date: Fri, 21 Mar 2025 18:09:25 +0200
From: Svyatoslav Ryhel <clamor95@...il.com>
To: Rob Herring <robh@...nel.org>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Thierry Reding <treding@...dia.com>, Jonathan Hunter <jonathanh@...dia.com>, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/3] dt-bindings: display: tegra: document EPP, ISP,
MPE and TSEC for Tegra114 and Tegra124
пт, 21 бер. 2025 р. о 18:02 Rob Herring <robh@...nel.org> пише:
>
> On Fri, Mar 14, 2025 at 09:45:55AM +0200, Svyatoslav Ryhel wrote:
> > The current EPP, ISP and MPE schemas are largely compatible with Tegra114
> > and Tegra124, requiring only minor adjustments. Additionally, the TSEC
> > schema for the Security engine, which is available from Tegra114 onwards,
> > is included.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> > ---
> > .../display/tegra/nvidia,tegra114-tsec.yaml | 66 +++++++++++++++++++
> > .../display/tegra/nvidia,tegra20-epp.yaml | 14 ++--
> > .../display/tegra/nvidia,tegra20-isp.yaml | 14 ++--
> > .../display/tegra/nvidia,tegra20-mpe.yaml | 18 +++--
> > 4 files changed, 99 insertions(+), 13 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
> > new file mode 100644
> > index 000000000000..c66ac6a6538e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
> > @@ -0,0 +1,66 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NVIDIA Tegra Security co-processor
> > +
> > +maintainers:
> > + - Svyatoslav Ryhel <clamor95@...il.com>
> > + - Thierry Reding <thierry.reding@...il.com>
> > +
> > +description: Tegra Security co-processor, an embedded security processor used
> > + mainly to manage the HDCP encryption and keys on the HDMI link.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - enum:
> > + - nvidia,tegra114-tsec
> > + - nvidia,tegra124-tsec
> > +
> > + - items:
> > + - const: nvidia,tegra132-tsec
> > + - const: nvidia,tegra124-tsec
>
> nvidia,tegra210-tsec appears to be about the same, already in use, and
> undocumented, so please add it to this binding.
>
Sure
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + reset-names:
> > + items:
> > + - const: tsec
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + operating-points-v2: true
> > +
> > + power-domains:
> > + items:
> > + - description: phandle to the core power domain
> > +
> > +additionalProperties: false
>
> required properties?
>
I will see what I can do about this.
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/tegra114-car.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + tsec@...00000 {
> > + compatible = "nvidia,tegra114-tsec";
> > + reg = <0x54500000 0x00040000>;
> > + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&tegra_car TEGRA114_CLK_TSEC>;
> > + resets = <&tegra_car TEGRA114_CLK_TSEC>;
> > + reset-names = "tsec";
> > + };
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