linux-kernel - [v5 3/4] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities

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Message-Id: <20250321163803.391056-4-18255117159@163.com>
Date: Sat, 22 Mar 2025 00:38:02 +0800
From: Hans Zhang <18255117159@....com>
To: lpieralisi@...nel.org
Cc: kw@...ux.com,
	manivannan.sadhasivam@...aro.org,
	robh@...nel.org,
	bhelgaas@...gle.com,
	jingoohan1@...il.com,
	thomas.richard@...tlin.com,
	linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Hans Zhang <18255117159@....com>
Subject: [v5 3/4] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities

Since the PCI core is now exposing generic APIs for the host bridges to
search for the PCIe capabilities, make use of them in the CDNS driver.

Signed-off-by: Hans Zhang <18255117159@....com>
---
Changes since v4:
https://lore.kernel.org/linux-pci/20250321101710.371480-4-18255117159@163.com/

- The patch subject and commit message were modified.

Changes since v2~v3:
https://lore.kernel.org/linux-pci/20250308133903.322216-1-18255117159@163.com/
https://lore.kernel.org/linux-pci/20250321040358.360755-4-18255117159@163.com/

- Introduce generic capability search functions

Changes since v1:
https://lore.kernel.org/linux-pci/20250123070935.1810110-1-18255117159@163.com

- Added calling the new API in PCI-Cadence ep.c.
- Add a commit message reason for adding the API.
---
 drivers/pci/controller/cadence/pcie-cadence.c | 25 +++++++++++++++++++
 drivers/pci/controller/cadence/pcie-cadence.h |  3 +++
 2 files changed, 28 insertions(+)

diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
index 204e045aed8c..329dab4ff813 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.c
+++ b/drivers/pci/controller/cadence/pcie-cadence.c
@@ -8,6 +8,31 @@
 
 #include "pcie-cadence.h"
 
+static u32 cdns_pcie_read_cfg(void *priv, int where, int size)
+{
+	struct cdns_pcie *pcie = priv;
+	u32 val;
+
+	if (size == 4)
+		val = readl(pcie->reg_base + where);
+	else if (size == 2)
+		val = readw(pcie->reg_base + where);
+	else if (size == 1)
+		val = readb(pcie->reg_base + where);
+
+	return val;
+}
+
+u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap)
+{
+	return pci_host_bridge_find_capability(pcie, cdns_pcie_read_cfg, cap);
+}
+
+u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap)
+{
+	return pci_host_bridge_find_ext_capability(pcie, cdns_pcie_read_cfg, cap);
+}
+
 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
 {
 	u32 delay = 0x3;
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index f5eeff834ec1..6f4981fccb94 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -557,6 +557,9 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 }
 #endif
 
+u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap);
+u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap);
+
 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
 
 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
-- 
2.25.1