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Message-ID: <20250321095556.91425-1-clamor95@gmail.com>
Date: Fri, 21 Mar 2025 11:55:53 +0200
From: Svyatoslav Ryhel <clamor95@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Svyatoslav Ryhel <clamor95@...il.com>
Cc: linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-pm@...r.kernel.org
Subject: [PATCH v1 0/3] clk: tegra: add DFLL support for Tegra 4
DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on
a ring oscillator and translates voltage changes into frequency
compensation changes needed to prevent the CPU from failing and is
essential for correct CPU frequency scaling.
Svyatoslav Ryhel (3):
drivers: cpufreq: add Tegra 4 support
drivers: clk: tegra: add DFLL support for Tegra 4
ARM: tegra: Add DFLL clock support on Tegra 4
arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 +++++++
drivers/clk/tegra/Kconfig | 2 +-
drivers/clk/tegra/clk-tegra114.c | 30 +++++-
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 104 +++++++++++++++++++++
drivers/clk/tegra/clk.h | 2 -
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/tegra124-cpufreq.c | 5 +-
include/dt-bindings/reset/tegra114-car.h | 13 +++
8 files changed, 182 insertions(+), 9 deletions(-)
create mode 100644 include/dt-bindings/reset/tegra114-car.h
--
2.43.0
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