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Message-ID: <CAJ9a7VjwKUgS-9gbpi--9+d6uvE4O8w+U4K+4t31Zo8BhoBSKg@mail.gmail.com> Date: Fri, 21 Mar 2025 14:00:10 +0000 From: Mike Leach <mike.leach@...aro.org> To: songchai <quic_songchai@...cinc.com> Cc: Suzuki K Poulose <suzuki.poulose@....com>, James Clark <james.clark@....com>, Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Andy Gross <agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, linux-kernel@...r.kernel.org, coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org Subject: Re: [PATCH v3 0/7] Provides support for Trigger Generation Unit Hi, On Fri, 21 Mar 2025 at 03:26, songchai <quic_songchai@...cinc.com> wrote: > > > On 3/7/2025 12:57 AM, Mike Leach wrote: > > Hi, > > > > On Thu, 27 Feb 2025 at 09:27, songchai <quic_songchai@...cinc.com> wrote: > >> Provide support for the TGU (Trigger Generation Unit), which can be > >> utilized to sense a plurality of signals and create a trigger into > >> the CTI or generate interrupts to processors once the input signal > >> meets the conditions. We can treat the TGU’s workflow as a flowsheet, > >> it has some “steps” regions for customization. In each step region, > >> we can set the signals that we want with priority in priority_group, set > >> the conditions in each step via condition_decode, and set the resultant > >> action by condition_select. Meanwhile, some TGUs (not all) also provide > >> timer/counter functionality. Based on the characteristics described > >> above, we consider the TGU as a helper in the CoreSight subsystem. > >> Its master device is the TPDM, which can transmit signals from other > >> subsystems, and we reuse the existing ports mechanism to link the TPDM to > >> the connected TGU. > >> > > I do not believe that his component is part of the Coresight subsystem. > > > > 1) It inputs multiple signals from the SoC to process and create an > > trigger event - however, it can do this irrespective of CoreSight > > trace being operational, especially where generating interrupts for > > processors, or triggers for other non-coresight components. It would > > appear that the TPDM can send output to more than just the TDPA which > > generates coresight trace packets - a previously undisclosed feature. > > TGU is a part the QPMDA(Qualcomm Performance Monitoring and > > Diagnostics Architecture ) library, and the signals it perceives are > from TPDM and connected > > through hardware. So it depends on the coresight-tpdm, and will not > work if the coresight > > tpdm is not operational. > As I understand it from reading many of the patches for this and other of the components, the QPMDA is a proprietary network of monitoring components across your SoCs, that can have an endpoint that generates CoreSight trace (from the TPDA). The nature of this network has not been specified - but it does seem that the TDPM can output to more than one device - perhaps some sort of internal bus runs between all the QPMDA devices. Is it possible that the TDPM can be programmed to output to the TGU, without trace being generated from the TPDA? If you enable just the TPDM and TGU, can you program the TGU to output triggers to CPU and other none-coresight devices, as implied in the binding descriptions? > > > > 2) The ports mechanism is a generic device tree mechanism, not > > something unique to the Coresight subsystem. > > Sure, Mike. As i mentioned above, the signals reach the TGU through > hardware.So the port > > mechanism here is not for the data transmission, but to confirm the > relationship of the TGU > > as a TPDM helper. > > > > > 3) The CTI trigger connection will be defined in devicetree under the > > CTI component, as this is the interface between this component and > > coresight. > > The TGU is utilized to sense a plurality of signals and create a trigger > into the CTI. > > It should be a trigger in for the targeting CTI. Could we configure the > targeting CTI's trigger_in > > and trigger_out instead of configuring in the devicetree? > You would need to make additional device tree entries in the relevant CTI for the input trigger from the TGU for the CTI driver to correctly display the source of the trigger. > > > > As such this seems more like a general performance and debug > > component, with optional inputs to the coresight trigger mechanisms, > > rather than being a coresight component itself. Other SoCs have > > non-coresight component inputs to CTIs. For example the PL011 serial > > device on Juno has a signal into one of the system CTIs. > > In addition to above, the TGU also have the coresight management > registers in its register region > > which is a character of coresight component. > These registers are not exposed in sysfs by your driver, nor are the values known, so it is difficult to know if they correctly follow the CoreSight 3.0 Architecture specification - ARM IHI 0029F; which defines the identification and discovery requirements that all CoreSight components must follow. These appear to be missing from your other devices listed in the coresight driver area - something we appear to have overlooked in previous driver reviews. The CTI / ETM and other ARM component coresight drivers all have a sysfs "mgmt" section that exposes these management registers. As I mentioned in my comments to the bindings in patch 1 - the Coresight visible component architecture and ID registers should be used to discover and identify the capabilities of components, such as in this case the number of steps/timers/triggers/priorities - and not need these values to be defined in the device tree. In this way, we remove the possibility of errors in a device tree leading to driver failure. Regards Mike > Based on these clarification, could we consider it as a coresight > component？ > > > >> Here is a detailed example to explain how to use the TGU: > >> > >> In this example, the TGU is configured to use 2 conditions, 2 steps, and > >> the timer. The goal is to look for one of two patterns which are generated > >> from TPDM, giving priority to one, and then generate a trigger once the > >> timer reaches a certain value. In other words, two conditions are used > >> for the first step to look for the two patterns, where the one with the > >> highest priority is used in the first condition. Then, in the second step, > >> the timer is enabled and set to be compared to the given value at each > >> clock cycle. These steps are better shown below. > >> > >> > >> |-----------------| > >> | | > >> | TPDM | > >> | | > >> |-----------------| > >> | > >> | > >> --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------ > >> | | | > >> | | |--------------------| | > >> | |---- ---> | | Go to next steps | | > >> | | | |--- ---> | Enable timer | | > >> | | v | | | | > >> | | |-----------------| | |--------------------| | > >> | | | | Yes | | | > >> | | | inputs==0xB | ----->| | <-------- | > >> | | | | | | No | | > >> | No | |-----------------| | v | | > >> | | | | |-----------------| | | > >> | | | | | | | | > >> | | | | | timer>=3 |-- | > >> | | v | | | | > >> | | |-----------------| | |-----------------| | > >> | | | | Yes | | | > >> | |--- | inputs==0xA | ----->| | Yes | > >> | | | | | > >> | |-----------------| v | > >> | |-----------------| | > >> | | | | > >> | | Trigger | | > >> | | | | > >> | |-----------------| | > >> | TGU | | > >> |--- --- --- --- --- --- --- --- --- --- --- --- --- --- |--- --- -- | > >> | > >> v > >> |-----------------| > >> |The controllers | > >> |which will use | > >> |triggers further | > >> |-----------------| > >> > >> steps: > >> 1. Reset TGU /*it will disable tgu and reset dataset*/ > >> - echo 1 > /sys/bus/coresight/devices/<tgu-name>/reset_tgu > >> > >> 2. Set the pattern match for priority0 to 0xA = 0b1010 and for > >> priority 1 to 0xB = 0b1011. > >> - echo 0x11113232 > /sys/bus/coresight/devices/<tgu-name>/step0_priority0/reg0 > >> - echo 0x11113233 > /sys/bus/coresight/devices/<tgu-name>/step0_priority1/reg0 > >> > >> Note: > >> Bit distribution diagram for each priority register > >> |-------------------------------------------------------------------| > >> | Bits | Field Nam | Description | > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 29:28 | SEL_BIT7_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 25:24 | SEL_BIT6_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 21:20 | SEL_BIT5_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 17:16 | SEL_BIT4_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 13:12 | SEL_BIT3_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 9:8 | SEL_BIT2_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 5:4 | SEL_BIT1_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> | | | 00 = bypass for OR output | > >> | 1:0 | SEL_BIT0_TYPE2 | 01 = bypass for AND output | > >> | | | 10 = sense input '0' is true| > >> | | | 11 = sense input '1' is true| > >> |-------------------------------------------------------------------| > >> These bits are used to identify the signals we want to sense, with > >> a maximum signal number of 140. For example, to sense the signal > >> 0xA (binary 1010), we set the value of bits 0 to 13 to 3232, which > >> represents 1010. The remaining bits are set to 1, as we want to use > >> AND gate to summarize all the signals we want to sense here. For > >> rising or falling edge detection of any input to the priority, set > >> the remaining bits to 0 to use an OR gate. > >> > >> 3. look for the pattern for priority_i i=0,1. > >> - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg0 > >> - echo 0x30 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg1 > >> > >> |-------------------------------------------------------------------------------| > >> | Bits | Field Nam | Description | > >> |-------------------------------------------------------------------------------| > >> | | |For each decoded condition, this | > >> | 24 | NOT |inverts the output. If the condition | > >> | | |decodes to true, and the NOT field | > >> | | |is '1', then the output is NOT true. | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | 21 | BC0_COMP_ACTIVE |comparator will be actively included in| > >> | | |the decoding of this particular | > >> | | |condition. | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | | |comparator will need to be 1 to affect | > >> | 20 | BC0_COMP_HIGH |the decoding of this condition. | > >> | | |Conversely, a '0' here requires a '0' | > >> | | |from the comparator | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | 17 | |comparator will be actively included in| > >> | | TC0_COMP_ACTIVE |the decoding of this particular | > >> | | |condition. | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | | |comparator will need to be 1 to affect | > >> | 16 | TC0_COMP_HIGH |the decoding of this particular | > >> | | |condition.Conversely, a 0 here | > >> | | |requires a '0' from the comparator | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from Priority_n | > >> | | |OR logic will be actively | > >> | 4n+3 | Priority_n_OR_ACTIVE|included in the decoding of | > >> | | (n=0,1,2,3) |this particular condition. | > >> | | | | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from Priority_n | > >> | | |will need to be '1' to affect the | > >> | 4n+2 | Priority_n_OR_HIGH |decoding of this particular | > >> | | (n=0,1,2,3) |condition. Conversely, a '0' here | > >> | | |requires a '0' from Priority_n OR logic| > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from Priority_n | > >> | | |AND logic will be actively | > >> | 4n+1 |Priority_n_AND_ACTIVE|included in the decoding of this | > >> | | (n=0,1,2,3) |particular condition. | > >> | | | | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from Priority_n | > >> | | |AND logic will need to be '1' to | > >> | 4n | Priority_n_AND_HIGH |affect the decoding of this | > >> | | (n=0,1,2,3) |particular condition. Conversely, | > >> | | |a '0' here requires a '0' from | > >> | | |Priority_n AND logic. | > >> |-------------------------------------------------------------------------------| > >> Since we use `priority_0` and `priority_1` with an AND output in step 2, we set `0x3` > >> and `0x30` here to activate them. > >> > >> 4. Set NEXT_STEP = 1 and TC0_ENABLE = 1 so that when the conditions > >> are met then the next step will be step 1 and the timer will be enabled. > >> - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg0 > >> - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg1 > >> > >> |-----------------------------------------------------------------------------| > >> | Bits | Field Nam | Description | > >> |-----------------------------------------------------------------------------| > >> | | |This field defines the next step the | > >> | 18:17 | NEXT_STEP |TGU will 'goto' for the associated | > >> | | |Condition and Step. | > >> |-----------------------------------------------------------------------------| > >> | | |For each possible output trigger | > >> | 13 | TRIGGER |available, set a '1' if you want | > >> | | |the trigger to go active for the | > >> | | |associated condition and Step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will cause BC0 to increment if the| > >> | 9 | BC0_INC |associated Condition is decoded for | > >> | | |this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will cause BC0 to decrement if the| > >> | 8 | BC0_DEC |associated Condition is decoded for | > >> | | |this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will clear BC0 count value to 0 if| > >> | 7 | BC0_CLEAR |the associated Condition is decoded | > >> | | |for this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will cause TC0 to increment until | > >> | 3 | TC0_ENABLE |paused or cleared if the associated | > >> | | |Condition is decoded for this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will cause TC0 to pause until | > >> | 2 | TC0_PAUSE |enabled if the associated Condition | > >> | | |is decoded for this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will clear TC0 count value to 0 | > >> | 1 | TC0_CLEAR |if the associated Condition is | > >> | | |decoded for this step. | > >> |-----------------------------------------------------------------------------| > >> | | |This will set the done signal to the | > >> | 0 | DONE |TGU FSM if the associated Condition | > >> | | |is decoded for this step. | > >> |-----------------------------------------------------------------------------| > >> Based on the distribution diagram, we set `0x20008` for `priority0` and `priority1` to > >> achieve "jump to step 1 and enable TC0" once the signal is sensed. > >> > >> 5. activate the timer comparison for this step. > >> - echo 0x30000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_decode/reg0 > >> > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | 17 | |comparator will be actively included in| > >> | | TC0_COMP_ACTIVE |the decoding of this particular | > >> | | |condition. | > >> |-------------------------------------------------------------------------------| > >> | | |When '1' the output from the associated| > >> | | |comparator will need to be 1 to affect | > >> | 16 | TC0_COMP_HIGH |the decoding of this particular | > >> | | |condition.Conversely, a 0 here | > >> | | |requires a '0' from the comparator | > >> |-------------------------------------------------------------------------------| > >> Accroding to the decode distribution diagram , we give 0x30000 here to set 16th&17th bit > >> to enable timer comparison. > >> > >> 6. Set the NEXT_STEP = 0 and TC0_PAUSE = 1 and TC0_CLEAR = 1 once the timer > >> has reached the given value. > >> - echo 0x6 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/reg0 > >> > >> 7. Enable Trigger 0 for TGU when the condition 0 is met in step1, > >> i.e. when the timer reaches 3. > >> - echo 0x2000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/default > >> > >> Note: > >> 1. 'default' register allows for establishing the resultant action for > >> the default condition > >> > >> 2. Trigger:For each possible output trigger available from > >> the Design document, there are three triggers: interrupts, CTI, > >> and Cross-TGU mapping.All three triggers can occur, but > >> the choice of which trigger to use depends on the user's > >> needs. > >> > >> 8. Compare the timer to 3 in step 1. > >> - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step1_timer/reg0 > >> > >> 9. enale tgu > >> - echo 1 > /sys/bus/coresight/devices/<tgu-name>/enable_tgu > >> > > If this is version 3 - where is the list of differences from versions 1 - 2? > My bad. Will add the previous change log in the next version. > > > >> Songwei Chai (7): > >> dt-bindings: arm: Add support for Coresight TGU trace > >> coresight: Add coresight TGU driver > >> coresight-tgu: Add signal priority support > >> coresight-tgu: Add TGU decode support > >> coresight-tgu: add support to configure next action > >> coresight-tgu: add timer/counter functionality for TGU > >> coresight-tgu: add reset node to initialize > >> > >> .../testing/sysfs-bus-coresight-devices-tgu | 51 ++ > >> .../bindings/arm/qcom,coresight-tgu.yaml | 135 ++++ > >> drivers/hwtracing/coresight/Kconfig | 11 + > >> drivers/hwtracing/coresight/Makefile | 1 + > >> drivers/hwtracing/coresight/coresight-tgu.c | 669 ++++++++++++++++++ > >> drivers/hwtracing/coresight/coresight-tgu.h | 242 +++++++ > >> 6 files changed, 1109 insertions(+) > >> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu > >> create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml > >> create mode 100644 drivers/hwtracing/coresight/coresight-tgu.c > >> create mode 100644 drivers/hwtracing/coresight/coresight-tgu.h > >> > > Regards > > > > > > Mike > > > > -- > > Mike Leach > > Principal Engineer, ARM Ltd. > > Manchester Design Centre. UK -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
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