linux-kernel - [PATCH] drm/bridge: chrontel-ch7033: Fix precedence bug in ch7033_bridge_mode

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Message-ID: <20c0422d-b4fc-4ec7-b3e5-4c4679f499f5@stanley.mountain>
Date: Fri, 21 Mar 2025 17:36:18 +0300
From: Dan Carpenter <dan.carpenter@...aro.org>
To: Lubomir Rintel <lkundrak@...sk>
Cc: Andrzej Hajda <andrzej.hajda@...el.com>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	Robert Foss <rfoss@...nel.org>,
	Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
	Jonas Karlman <jonas@...boo.se>,
	Jernej Skrabec <jernej.skrabec@...il.com>,
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
	Maxime Ripard <mripard@...nel.org>,
	Thomas Zimmermann <tzimmermann@...e.de>,
	David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
	Sam Ravnborg <sam@...nborg.org>, dri-devel@...ts.freedesktop.org,
	linux-kernel@...r.kernel.org, kernel-janitors@...r.kernel.org
Subject: [PATCH] drm/bridge: chrontel-ch7033: Fix precedence bug in
 ch7033_bridge_mode_set()

The problem is that the bitwise OR operation has higher precedence than
the ternary expression.  The existing code will either set
HPO_I, VPO_I, or "mode->clock >> 16" but not a combination of the three
which is what we want.

Fixes: e7f12054a1b9 ("drm/bridge: chrontel-ch7033: Add a new driver")
Signed-off-by: Dan Carpenter <dan.carpenter@...aro.org>
---
>From static analysis.  Not tested!

 drivers/gpu/drm/bridge/chrontel-ch7033.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c
index da17f0978a79..1b858a8ced57 100644
--- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -404,9 +404,9 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
 	/* Input clock and sync polarity. */
 	regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
 	regmap_update_bits(priv->regmap, 0x19, HPO_I | VPO_I | GCLKFREQ,
-			   (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0 |
-			   (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0 |
-			   mode->clock >> 16);
+			   ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0) |
+			   ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0) |
+			   (mode->clock >> 16));
 	regmap_write(priv->regmap, 0x1a, mode->clock >> 8);
 	regmap_write(priv->regmap, 0x1b, mode->clock);
 
@@ -427,8 +427,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
 
 	/* Output sync polarity. */
 	regmap_update_bits(priv->regmap, 0x2e, HPO_O | VPO_O,
-			   (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0 |
-			   (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0);
+			   ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0) |
+			   ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0));
 
 	/* HDMI horizontal output timing. */
 	regmap_update_bits(priv->regmap, 0x54, HWO_HDMI_HI | HOO_HDMI_HI,
-- 
2.47.2