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Message-ID: <j3qw4zmopulpn3iqq5wsjt6dbs4z3micoeoxkw3354txkx22ml@67ip5sfo6wwd>
Date: Mon, 24 Mar 2025 22:48:23 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: Frank Li <Frank.Li@....com>, Rob Herring <robh@...nel.org>,
Saravana Kannan <saravanak@...gle.com>, Jingoo Han <jingoohan1@...il.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof Wilczyński <kw@...ux.com>,
Richard Zhu <hongxing.zhu@....com>, Lucas Stach <l.stach@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Niklas Cassel <cassel@...nel.org>,
Pengutronix Kernel Team <kernel@...gutronix.de>, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, imx@...ts.linux.dev,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH v12 05/13] PCI: dwc: Add dw_pcie_parent_bus_offset()
On Sat, Mar 15, 2025 at 03:15:40PM -0500, Bjorn Helgaas wrote:
> From: Frank Li <Frank.Li@....com>
>
> Return the offset from CPU physical address to the parent bus address of
> the specified element of the devicetree 'reg' property.
>
> [bhelgaas: return offset, split .cpu_addr_fixup() checking and debug to
> separate patch]
> Link: https://lore.kernel.org/r/20250313-pci_fixup_addr-v11-5-01d2313502ab@nxp.com
> Signed-off-by: Frank Li <Frank.Li@....com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 23 ++++++++++++++++++++
> drivers/pci/controller/dwc/pcie-designware.h | 3 +++
> 2 files changed, 26 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 9d0a5f75effc..0a35e36da703 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -16,6 +16,7 @@
> #include <linux/gpio/consumer.h>
> #include <linux/ioport.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/sizes.h>
> #include <linux/types.h>
> @@ -1105,3 +1106,25 @@ void dw_pcie_setup(struct dw_pcie *pci)
>
> dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> }
> +
> +resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
> + const char *reg_name,
> + resource_size_t cpu_phy_addr)
> +{
s/cpu_phy_addr/cpu_phys_addr/g
'phy' usually refers to the physical layer IP block. So 'cpu_phy_addr' sounds
like the address of the CPU PHY.
> + struct device *dev = pci->dev;
> + struct device_node *np = dev->of_node;
> + int index;
> + u64 reg_addr;
> +
> + /* Look up reg_name address on parent bus */
'parent bus' is not accurate as the below code checks for the 'reg_name' in
current PCI controller node.
> + index = of_property_match_string(np, "reg-names", reg_name);
> +
> + if (index < 0) {
> + dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
Both of these callers are checking for the existence of the 'reg_name' property
before calling this API. So this check seems to be redundant (for now).
- Mani
--
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