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Message-ID: <0df07b23-4821-4b7d-85d8-dfaa7516fbc4@quicinc.com>
Date: Mon, 24 Mar 2025 15:11:58 +0800
From: "Wenbin Yao (Consultant)" <quic_wenbyao@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
CC: <andersson@...nel.org>, <konradybcio@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <catalin.marinas@....com>,
<will@...nel.org>, <quic_qianyu@...cinc.com>, <sfr@...b.auug.org.au>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: x1e80100: add bus topology for
PCIe domain 3
On 3/22/2025 1:19 AM, Dmitry Baryshkov wrote:
> On Thu, Mar 20, 2025 at 01:55:01PM +0800, Wenbin Yao wrote:
>> From: Qiang Yu <quic_qianyu@...cinc.com>
>>
>> Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot
>> voltage rails can be described under this node in the board's dts.
>>
>> Signed-off-by: Qiang Yu <quic_qianyu@...cinc.com>
>> Signed-off-by: Wenbin Yao <quic_wenbyao@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 46b79fce9..32e8d400a 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -3287,6 +3287,16 @@ opp-128000000 {
>> opp-peak-kBps = <15753000 1>;
>> };
>> };
>> + pcie3port: pcie@0 {
> Empty line between nodes, please.
Will fix in the next version.
>
>> + device_type = "pci";
>> + compatible = "pciclass,0604";
>> + reg = <0x0 0x0 0x0 0x0 0x0>;
>> + bus-range = <0x01 0xff>;
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges;
>> + };
>> };
>>
>> pcie3_phy: phy@...0000 {
>> --
>> 2.34.1
>>
--
With best wishes
Wenbin
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