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Message-ID: <2cf735da-9f20-4372-8b08-0b40c335ba6b@ixit.cz>
Date: Mon, 24 Mar 2025 13:58:55 +0100
From: David Heidelberg <david@...t.cz>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>, Yong Wu <yong.wu@...iatek.com>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Maxime Ripard <mripard@...nel.org>, iommu@...ts.linux.dev,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-mediatek@...ts.infradead.org, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: iommu: Correct indentation and style in DTS
example
On 24/03/2025 13:52, Krzysztof Kozlowski wrote:
> DTS example in the bindings should be indented with 2- or 4-spaces and
> aligned with opening '- |', so correct any differences like 3-spaces or
> mixtures 2- and 4-spaces in one binding. While re-indenting, drop
> unused labels.
>
> No functional changes here, but saves some comments during reviews of
> new patches built on existing code.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
> .../iommu/allwinner,sun50i-h6-iommu.yaml | 24 ++--
> .../bindings/iommu/arm,smmu-v3.yaml | 20 ++--
> .../devicetree/bindings/iommu/arm,smmu.yaml | 104 +++++++++---------
> .../bindings/iommu/mediatek,iommu.yaml | 18 +--
> .../bindings/iommu/qcom,apq8064-iommu.yaml | 20 ++--
> 5 files changed, 92 insertions(+), 94 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
> index a8409db4a3e3..ad51ace9ca09 100644
> --- a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
> @@ -48,19 +48,19 @@ additionalProperties: false
>
> examples:
> - |
> - #include <dt-bindings/interrupt-controller/arm-gic.h>
> - #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
>
> - #include <dt-bindings/clock/sun50i-h6-ccu.h>
> - #include <dt-bindings/reset/sun50i-h6-ccu.h>
> + #include <dt-bindings/clock/sun50i-h6-ccu.h>
> + #include <dt-bindings/reset/sun50i-h6-ccu.h>
>
> - iommu: iommu@...0000 {
> - compatible = "allwinner,sun50i-h6-iommu";
> - reg = <0x030f0000 0x10000>;
> - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ccu CLK_BUS_IOMMU>;
> - resets = <&ccu RST_BUS_IOMMU>;
> - #iommu-cells = <1>;
> - };
> + iommu@...0000 {
> + compatible = "allwinner,sun50i-h6-iommu";
> + reg = <0x030f0000 0x10000>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_IOMMU>;
> + resets = <&ccu RST_BUS_IOMMU>;
> + #iommu-cells = <1>;
> + };
>
> ...
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index 75fcf4cb52d9..36b31197c908 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -82,14 +82,14 @@ examples:
> #include <dt-bindings/interrupt-controller/irq.h>
>
> iommu@...00000 {
> - compatible = "arm,smmu-v3";
> - reg = <0x2b400000 0x20000>;
> - interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
> - <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
> - <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
> - <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
> - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> - dma-coherent;
> - #iommu-cells = <1>;
> - msi-parent = <&its 0xff0000>;
> + compatible = "arm,smmu-v3";
> + reg = <0x2b400000 0x20000>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> + dma-coherent;
> + #iommu-cells = <1>;
> + msi-parent = <&its 0xff0000>;
> };
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index 7b9d5507d6cc..5b56e4f9d106 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -621,73 +621,71 @@ examples:
> - |+
> /* SMMU with stream matching or stream indexing */
> smmu1: iommu@...e0000 {
> - compatible = "arm,smmu-v1";
> - reg = <0xba5e0000 0x10000>;
> - #global-interrupts = <2>;
> - interrupts = <0 32 4>,
> - <0 33 4>,
> - <0 34 4>, /* This is the first context interrupt */
> - <0 35 4>,
> - <0 36 4>,
> - <0 37 4>;
> - #iommu-cells = <1>;
> + compatible = "arm,smmu-v1";
> + reg = <0xba5e0000 0x10000>;
> + #global-interrupts = <2>;
> + interrupts = <0 32 4>,
> + <0 33 4>,
> + <0 34 4>, /* This is the first context interrupt */
> + <0 35 4>,
> + <0 36 4>,
> + <0 37 4>;
> + #iommu-cells = <1>;
> };
>
> /* device with two stream IDs, 0 and 7 */
> master1 {
> - iommus = <&smmu1 0>,
> - <&smmu1 7>;
> + iommus = <&smmu1 0>,
> + <&smmu1 7>;
> };
>
>
> /* SMMU with stream matching */
> smmu2: iommu@...f0000 {
> - compatible = "arm,smmu-v1";
> - reg = <0xba5f0000 0x10000>;
> - #global-interrupts = <2>;
> - interrupts = <0 38 4>,
> - <0 39 4>,
> - <0 40 4>, /* This is the first context interrupt */
> - <0 41 4>,
> - <0 42 4>,
> - <0 43 4>;
> - #iommu-cells = <2>;
> + compatible = "arm,smmu-v1";
> + reg = <0xba5f0000 0x10000>;
> + #global-interrupts = <2>;
> + interrupts = <0 38 4>,
> + <0 39 4>,
> + <0 40 4>, /* This is the first context interrupt */
> + <0 41 4>,
> + <0 42 4>,
> + <0 43 4>;
> + #iommu-cells = <2>;
> };
>
> /* device with stream IDs 0 and 7 */
> master2 {
> - iommus = <&smmu2 0 0>,
> - <&smmu2 7 0>;
> + iommus = <&smmu2 0 0>,
> + <&smmu2 7 0>;
> };
>
> /* device with stream IDs 1, 17, 33 and 49 */
> master3 {
> - iommus = <&smmu2 1 0x30>;
> + iommus = <&smmu2 1 0x30>;
> };
>
>
> /* ARM MMU-500 with 10-bit stream ID input configuration */
> smmu3: iommu@...00000 {
> - compatible = "arm,mmu-500", "arm,smmu-v2";
> - reg = <0xba600000 0x10000>;
> - #global-interrupts = <2>;
> - interrupts = <0 44 4>,
> - <0 45 4>,
> - <0 46 4>, /* This is the first context interrupt */
> - <0 47 4>,
> - <0 48 4>,
> - <0 49 4>;
> - #iommu-cells = <1>;
> - /* always ignore appended 5-bit TBU number */
> - stream-match-mask = <0x7c00>;
> + compatible = "arm,mmu-500", "arm,smmu-v2";
> + reg = <0xba600000 0x10000>;
> + #global-interrupts = <2>;
> + interrupts = <0 44 4>,
> + <0 45 4>,
> + <0 46 4>, /* This is the first context interrupt */
> + <0 47 4>,
> + <0 48 4>,
> + <0 49 4>;
If you want to squash another change,
0 xx 4
to
GIC_SPI xx IRQ_TYPE_LEVEL_HIGH
anyway, with or without:
Reviewed-by: David Heidelberg <david@...t.cz>
> + #iommu-cells = <1>;
> + /* always ignore appended 5-bit TBU number */
> + stream-match-mask = <0x7c00>;
> };
>
> bus {
> - /* bus whose child devices emit one unique 10-bit stream
> - ID each, but may master through multiple SMMU TBUs */
> - iommu-map = <0 &smmu3 0 0x400>;
> -
> -
> + /* bus whose child devices emit one unique 10-bit stream
> + ID each, but may master through multiple SMMU TBUs */
> + iommu-map = <0 &smmu3 0 0x400>;
> };
>
> - |+
> @@ -695,17 +693,17 @@ examples:
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> smmu4: iommu@...000 {
> - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> - reg = <0xd00000 0x10000>;
> + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> + reg = <0xd00000 0x10000>;
>
> - #global-interrupts = <1>;
> - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
> - #iommu-cells = <1>;
> - power-domains = <&mmcc 0>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
> + #iommu-cells = <1>;
> + power-domains = <&mmcc 0>;
>
> - clocks = <&mmcc 123>,
> - <&mmcc 124>;
> - clock-names = "bus", "iface";
> + clocks = <&mmcc 123>,
> + <&mmcc 124>;
> + clock-names = "bus", "iface";
> };
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index ea6b0f5f24de..1eac27893b03 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -218,13 +218,13 @@ examples:
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> iommu: iommu@...05000 {
> - compatible = "mediatek,mt8173-m4u";
> - reg = <0x10205000 0x1000>;
> - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&infracfg CLK_INFRA_M4U>;
> - clock-names = "bclk";
> - mediatek,infracfg = <&infracfg>;
> - mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> - <&larb3>, <&larb4>, <&larb5>;
> - #iommu-cells = <1>;
> + compatible = "mediatek,mt8173-m4u";
> + reg = <0x10205000 0x1000>;
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_INFRA_M4U>;
> + clock-names = "bclk";
> + mediatek,infracfg = <&infracfg>;
> + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> + <&larb3>, <&larb4>, <&larb5>;
> + #iommu-cells = <1>;
> };
> diff --git a/Documentation/devicetree/bindings/iommu/qcom,apq8064-iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,apq8064-iommu.yaml
> index 9f83f851e61a..aaecad32dc9d 100644
> --- a/Documentation/devicetree/bindings/iommu/qcom,apq8064-iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/qcom,apq8064-iommu.yaml
> @@ -65,14 +65,14 @@ examples:
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> iommu@...0000 {
> - compatible = "qcom,apq8064-iommu";
> - reg = <0x07500000 0x100000>;
> - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clk SMMU_AHB_CLK>,
> - <&clk MDP_AXI_CLK>;
> - clock-names = "smmu_pclk",
> - "iommu_clk";
> - #iommu-cells = <1>;
> - qcom,ncb = <2>;
> + compatible = "qcom,apq8064-iommu";
> + reg = <0x07500000 0x100000>;
> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk SMMU_AHB_CLK>,
> + <&clk MDP_AXI_CLK>;
> + clock-names = "smmu_pclk",
> + "iommu_clk";
> + #iommu-cells = <1>;
> + qcom,ncb = <2>;
> };
--
David Heidelberg
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