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Message-ID: <CAFULd4ZbYmwTOR0vc8+Xiq8uPgqbte=ruKVGiKKngjHmkNunFw@mail.gmail.com>
Date: Tue, 25 Mar 2025 18:17:01 +0100
From: Uros Bizjak <ubizjak@...il.com>
To: Borislav Petkov <bp@...en8.de>
Cc: x86@...nel.org, linux-kernel@...r.kernel.org,
Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...nel.org>,
Dave Hansen <dave.hansen@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>
Subject: Re: [PATCH -tip 1/2] x86/hweight: Fix false output register
dependency of POPCNT insn
On Tue, Mar 25, 2025 at 6:10 PM Borislav Petkov <bp@...en8.de> wrote:
>
> On Tue, Mar 25, 2025 at 05:48:37PM +0100, Uros Bizjak wrote:
> > +/*
> > + * On Sandy/Ivy Bridge and later Intel processors, the POPCNT instruction
> > + * appears to have a false dependency on the destination register. Even
> > + * though the instruction only writes to it, the instruction will wait
> > + * until destination is ready before executing. This false dependency
> > + * was fixed for Cannon Lake (and later) processors.
>
> Any official documentation about that?
Please see [1], errata 026.
[1] https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/8th-gen-core-spec-update.pdf
>
> Any performance numbers to justify that change?
There is a lot of performance analysis at [2] and [3].
[2] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62011
[3] https://stackoverflow.com/questions/25078285/replacing-a-32-bit-loop-counter-with-64-bit-introduces-crazy-performance-deviati
> Because if it doesn't matter, why do it in the first place? Especially if
> you're doing this XORing now for *everyone* - not just the affected parties.
Thanks,
Uros.
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