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Message-ID: <20250325175911.GGZ-Lu75TMFAML7gNf@fat_crate.local>
Date: Tue, 25 Mar 2025 18:59:11 +0100
From: Borislav Petkov <bp@...en8.de>
To: Uros Bizjak <ubizjak@...il.com>
Cc: x86@...nel.org, linux-kernel@...r.kernel.org,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...nel.org>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	"H. Peter Anvin" <hpa@...or.com>
Subject: Re: [PATCH 2/2] x86/bitops: Fix false output register dependency of
 TZCNT insn

On Tue, Mar 25, 2025 at 06:52:02PM +0100, Uros Bizjak wrote:
> On Haswell and later Intel processors, the TZCNT instruction appears
> to have a false dependency on the destination register. Even though
> the instruction only writes to it, the instruction will wait until
> destination is ready before executing. This false dependency
> was fixed for Skylake (and later) processors.
> 
> Fix false dependency by clearing the destination register first.

Same questions as about the POPCNT patch.

-- 
Regards/Gruss,
    Boris.

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