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Message-ID: <5hkzuqptaor4v5fc7ljxb36zdipeg67lsjfkcah5fkxfyyjt6e@oknqdtbwjitj>
Date: Tue, 25 Mar 2025 23:59:14 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: Frank Li <Frank.Li@....com>, Rob Herring <robh@...nel.org>,
Saravana Kannan <saravanak@...gle.com>, Jingoo Han <jingoohan1@...il.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof Wilczyński <kw@...ux.com>,
Richard Zhu <hongxing.zhu@....com>, Lucas Stach <l.stach@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Niklas Cassel <cassel@...nel.org>,
Pengutronix Kernel Team <kernel@...gutronix.de>, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, imx@...ts.linux.dev,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH v12 05/13] PCI: dwc: Add dw_pcie_parent_bus_offset()
On Mon, Mar 24, 2025 at 01:28:27PM -0500, Bjorn Helgaas wrote:
> On Mon, Mar 24, 2025 at 10:48:23PM +0530, Manivannan Sadhasivam wrote:
> > On Sat, Mar 15, 2025 at 03:15:40PM -0500, Bjorn Helgaas wrote:
> > > From: Frank Li <Frank.Li@....com>
> > >
> > > Return the offset from CPU physical address to the parent bus address of
> > > the specified element of the devicetree 'reg' property.
>
> > > +resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
> > > + const char *reg_name,
> > > + resource_size_t cpu_phy_addr)
> > > +{
> >
> > s/cpu_phy_addr/cpu_phys_addr/g
>
> Fixed, thanks!
>
> > > + struct device *dev = pci->dev;
> > > + struct device_node *np = dev->of_node;
> > > + int index;
> > > + u64 reg_addr;
> > > +
> > > + /* Look up reg_name address on parent bus */
> >
> > 'parent bus' is not accurate as the below code checks for the 'reg_name' in
> > current PCI controller node.
>
> We want the address of "reg_name" on the node's primary side. We've
> been calling that the "parent bus address", I guess because it's the
> address on the "parent bus" of the node.
>
Yeah, 'parent bus address' sounds bogus to me. 'ranges' property is described
as:
ranges = <child_addr parent_addr child_size>
Here, child_addr refers to the PCIe host controller's view of the address space
and parent_addr refers to the CPU's view of the address space.
So the register address described in the PCIe controller node is not a 'parent
bus address'.
> I'm not sure what the best term is for this. Do you have a
> suggestion?
>
We are just extracting the offset between translated (cpu_phy_addr) and
untranslated (reg_addr) addresses of a specific register. Maybe the function
should just return the 'untranslated address' and the caller should compute the
offset to make it simple?
> If "parent bus address" is the wrong term, maybe we need to rename
> dw_pcie_parent_bus_offset() itself?
>
Yes!
> Currently we pass in cpu_phys_addr, but this function doesn't need it
> except for the debug code added later. I would really rather have
> something like this in the callers:
>
> pci->parent_bus_offset = pp->cfg0_base -
> dw_pcie_parent_bus_addr(pci, "config");
>
I agree. This should become, dw_pcie_get_untranslated_addr().
> because then the offset is computed sort of at the same level where
> it's used, and a grep for "cfg0_base" would find both the set and the
> use and they would be easy to match up.
>
> > > + index = of_property_match_string(np, "reg-names", reg_name);
> > > +
> > > + if (index < 0) {
> > > + dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
> >
> > Both of these callers are checking for the existence of the
> > 'reg_name' property before calling this API. So this check seems to
> > be redundant (for now).
>
> True, but I don't see a way to enforce the caller checks. I don't
> like the idea of calling of_property_read_reg(np, index, ...) where we
> have to look the caller to verify that "index" is valid.
>
Ok.
- Mani
--
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