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Message-Id: <20250325121624.523258-11-guoren@kernel.org>
Date: Tue, 25 Mar 2025 08:15:51 -0400
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Subject: [RFC PATCH V3 10/43] rv64ilp32_abi: riscv: Update SATP.MODE.ASID width
From: "Guo Ren (Alibaba DAMO Academy)" <guoren@...nel.org>
The RV32 employs 9-bit asid_bits due to CSR's xlen=32 constraint,
whereas RV64ILP32 ABI, rooted in RV64 ISA, features a 64-bit
satp CSR. Hence, for rv64ilp32 abi, the exact asid mechanism as
in 64-bit architecture is adopted.
Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@...nel.org>
---
arch/riscv/mm/context.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
index 4abe3de23225..c3f9926d9337 100644
--- a/arch/riscv/mm/context.c
+++ b/arch/riscv/mm/context.c
@@ -226,14 +226,18 @@ static inline void set_mm(struct mm_struct *prev,
static int __init asids_init(void)
{
- unsigned long asid_bits, old;
+ xlen_t asid_bits, old;
/* Figure-out number of ASID bits in HW */
old = csr_read(CSR_SATP);
asid_bits = old | (SATP_ASID_MASK << SATP_ASID_SHIFT);
csr_write(CSR_SATP, asid_bits);
asid_bits = (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK;
- asid_bits = fls_long(asid_bits);
+#if __riscv_xlen == 64
+ asid_bits = fls64(asid_bits);
+#else
+ asid_bits = fls(asid_bits);
+#endif
csr_write(CSR_SATP, old);
/*
@@ -265,9 +269,9 @@ static int __init asids_init(void)
static_branch_enable(&use_asid_allocator);
pr_info("ASID allocator using %lu bits (%lu entries)\n",
- asid_bits, num_asids);
+ (ulong)asid_bits, num_asids);
} else {
- pr_info("ASID allocator disabled (%lu bits)\n", asid_bits);
+ pr_info("ASID allocator disabled (%lu bits)\n", (ulong)asid_bits);
}
return 0;
--
2.40.1
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