linux-kernel - Re: [PATCH 2/6] PCI: cadence: Add header support for PCIe next generation controllers

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Message-ID: <2ab4bf45-5bfd-48b0-bb5f-262d60c6f507@cixtech.com>
Date: Tue, 25 Mar 2025 11:12:37 +0800
From: Hans Zhang <hans.zhang@...tech.com>
To: Manikandan Karunakaran Pillai <mpillai@...ence.com>,
 "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
 "manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>,
 "bhelgaas@...gle.com" <bhelgaas@...gle.com>, "kw@...ux.com" <kw@...ux.com>,
 "robh@...nel.org" <robh@...nel.org>,
 "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
Subject: Re: [PATCH 2/6] PCI: cadence: Add header support for PCIe next
 generation controllers



On 2025/3/24 18:09, hans.zhang wrote:
>> + * High Performance Architecture(HPA) PCIe controller register
>> + */
>> +#define CDNS_PCIE_HPA_IP_REG_BANK              0x01000000
>> +#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK     0x01003C00
>> +#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON     0x01020000
>> +/*
>> + * Address Translation Registers(HPA)
>> + */
>> +#define CDNS_PCIE_HPA_AXI_SLAVE                 0x03000000
>> +#define CDNS_PCIE_HPA_AXI_MASTER                0x03002000
> 
> Hi Manikandan,
> 
> Can you change this part of the code to look like this?
> 
> #define CDNS_PCIE_HPA_IP_REG_BANK(a)              (a)
> #define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK(a)     (a)
> #define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON(a)     (a)
> #define CDNS_PCIE_HPA_AXI_SLAVE(a)                (a)
> #define CDNS_PCIE_HPA_AXI_MASTER(a)               (a)
> 
> 
> 
> The offset we designed is: (Cixtech)
> #define CDNS_PCIE_HPA_IP_REG_BANK 0x1000
> #define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x4c00
> #define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0xf000
> #define CDNS_PCIE_HPA_AXI_SLAVE 0x9000
> #define CDNS_PCIE_HPA_AXI_MASTER 0xb000
> #define CDNS_PCIE_HPA_AXI_HLS_REGISTERS 0xc000
> #define CDNS_PCIE_HPA_DTI_REGISTERS 0xd000
> #define CDNS_PCIE_HPA_AXI_RAS_REGISTERS 0xe000
> #define CDNS_PCIE_HPA_DMA_BASE 0xf400
> #define CDNS_PCIE_HPA_DMA_COMMON_BASE 0xf800
> 
> 
> The original register bank consumed at least 48MB address space which is 
> begin from 0x0000_0000 to 0x03020000. Because there is unoccupied 
> address space between every two register banks , our hardware remaps the 
> registers to a smaller address space which means the register bank 
> offset address is changed by custormer. So, we cannot utilise the common 
> code directly without rewriting the function.
> 
> 
> We submit and pull a Cadence case: #46872873
> 
> We will also reply to you in the case.

Reply from Cadence case Manikandan:
Another option I can propose is to pass these values through the DTS 
file … (Hopefully that would be lesser changes)

Hans:
I agree to get it through the DTS attribute, please modify it, so as to 
be more flexible. This offset value may be modified when RTL is integrated.

Best regards,
Hans