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Message-ID: <Z-QwQNmWPIRyVyPg@antec>
Date: Wed, 26 Mar 2025 16:50:08 +0000
From: Stafford Horne <shorne@...il.com>
To: Sahil Siddiq <icegambit91@...il.com>
Cc: jonas@...thpole.se, stefan.kristiansson@...nalahti.fi,
sahilcdq@...ton.me, linux-openrisc@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce
duplication
On Mon, Mar 24, 2025 at 01:25:42AM +0530, Sahil Siddiq wrote:
> The "cpuinfo_or1k" structure currently has identical data members for
> different cache components.
>
> Remove these fields out of struct cpuinfo_or1k and into its own struct.
> This reduces duplication while keeping cpuinfo_or1k extensible so more
> cache descriptors can be added in the future.
>
> Also add a new field "sets" to the new structure.
>
> Signed-off-by: Sahil Siddiq <sahilcdq@...ton.me>
This looks ok to me.
> ---
> Changes from v1/v2 -> v3:
> - arch/openrisc/kernel/setup.c:
> (print_cpuinfo):
> 1. Cascade changes made to struct cpuinfo_or1k.
> 2. These lines are ultimately shifted to the new file created in
> patch #3.
> (setup_cpuinfo): Likewise.
> (show_cpuinfo): Likewise.
>
> arch/openrisc/include/asm/cpuinfo.h | 16 +++++-----
> arch/openrisc/kernel/setup.c | 45 ++++++++++++++---------------
> 2 files changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
> index 5e4744153d0e..82f5d4c06314 100644
> --- a/arch/openrisc/include/asm/cpuinfo.h
> +++ b/arch/openrisc/include/asm/cpuinfo.h
> @@ -15,16 +15,18 @@
> #ifndef __ASM_OPENRISC_CPUINFO_H
> #define __ASM_OPENRISC_CPUINFO_H
>
> +struct cache_desc {
> + u32 size;
> + u32 sets;
> + u32 block_size;
> + u32 ways;
> +};
> +
> struct cpuinfo_or1k {
> u32 clock_frequency;
>
> - u32 icache_size;
> - u32 icache_block_size;
> - u32 icache_ways;
> -
> - u32 dcache_size;
> - u32 dcache_block_size;
> - u32 dcache_ways;
> + struct cache_desc icache;
> + struct cache_desc dcache;
>
> u16 coreid;
> };
> diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
> index be56eaafc8b9..66207cd7bb9e 100644
> --- a/arch/openrisc/kernel/setup.c
> +++ b/arch/openrisc/kernel/setup.c
> @@ -115,16 +115,16 @@ static void print_cpuinfo(void)
>
> if (upr & SPR_UPR_DCP)
> printk(KERN_INFO
> - "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
> - cpuinfo->dcache_size, cpuinfo->dcache_block_size,
> - cpuinfo->dcache_ways);
> + "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
> + cpuinfo->dcache.size, cpuinfo->dcache.block_size,
> + cpuinfo->dcache.sets, cpuinfo->dcache.ways);
> else
> printk(KERN_INFO "-- dcache disabled\n");
> if (upr & SPR_UPR_ICP)
> printk(KERN_INFO
> - "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
> - cpuinfo->icache_size, cpuinfo->icache_block_size,
> - cpuinfo->icache_ways);
> + "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
> + cpuinfo->icache.size, cpuinfo->icache.block_size,
> + cpuinfo->icache.sets, cpuinfo->icache.ways);
> else
> printk(KERN_INFO "-- icache disabled\n");
>
> @@ -156,7 +156,6 @@ void __init setup_cpuinfo(void)
> {
> struct device_node *cpu;
> unsigned long iccfgr, dccfgr;
> - unsigned long cache_set_size;
> int cpu_id = smp_processor_id();
> struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
>
> @@ -165,18 +164,18 @@ void __init setup_cpuinfo(void)
> panic("Couldn't find CPU%d in device tree...\n", cpu_id);
>
> iccfgr = mfspr(SPR_ICCFGR);
> - cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
> - cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
> - cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
> - cpuinfo->icache_size =
> - cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
> + cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
> + cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
> + cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
> + cpuinfo->icache.size =
> + cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
>
> dccfgr = mfspr(SPR_DCCFGR);
> - cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
> - cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
> - cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
> - cpuinfo->dcache_size =
> - cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
> + cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
> + cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
> + cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
> + cpuinfo->dcache.size =
> + cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
>
> if (of_property_read_u32(cpu, "clock-frequency",
> &cpuinfo->clock_frequency)) {
> @@ -320,14 +319,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
> seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
> }
> seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
> - seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
> + seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
> seq_printf(m, "dcache block size\t: %d bytes\n",
> - cpuinfo->dcache_block_size);
> - seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
> - seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
> + cpuinfo->dcache.block_size);
> + seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
> + seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
> seq_printf(m, "icache block size\t: %d bytes\n",
> - cpuinfo->icache_block_size);
> - seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
> + cpuinfo->icache.block_size);
> + seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
> seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
> 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
> 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
> --
> 2.48.1
>
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