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Message-ID: <20250326022811.3090688-2-sai.krishna.musham@amd.com>
Date: Wed, 26 Mar 2025 07:58:10 +0530
From: Sai Krishna Musham <sai.krishna.musham@....com>
To: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
<manivannan.sadhasivam@...aro.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <cassel@...nel.org>
CC: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <michal.simek@....com>,
<bharat.kumar.gogada@....com>, <thippeswamy.havalige@....com>,
<sai.krishna.musham@....com>
Subject: [PATCH v6 1/2] dt-bindings: PCI: xilinx-cpm: Add reset-gpios for PCIe RP PERST#
Introduce `reset-gpios` property to enable GPIO-based control of
the PCIe RP PERST# signal, generating assert and deassert signals.
Traditionally, the reset was managed in hardware and enabled during
initialization. With this patch set, the reset will be handled by the
driver. Consequently, the `reset-gpios` property must be explicitly
provided to ensure proper functionality.
Add CPM clock and reset control registers base (`cpm_crx`) to handle
PCIe IP reset along with PCIe RP PERST# to avoid Link Training errors.
Signed-off-by: Sai Krishna Musham <sai.krishna.musham@....com>
---
Changes for v6:
- Resolve ABI break.
- Update commit message.
Changes for v5:
- Remove `reset-gpios` property from required as it is already present
in pci-bus-common.yaml
- Update commit message
Changes for v4:
- Add CPM clock and reset control registers base to handle PCIe IP
reset.
- Update commit message.
Changes for v3:
- None
Changes for v2:
- Add define from include/dt-bindings/gpio/gpio.h for PERST# polarity
- Update commit message
---
.../bindings/pci/xilinx-versal-cpm.yaml | 72 ++++++++++++++-----
1 file changed, 55 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index d674a24c8ccc..26e9cea41889 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -9,9 +9,6 @@ title: CPM Host Controller device tree for Xilinx Versal SoCs
maintainers:
- Bharat Kumar Gogada <bharat.kumar.gogada@....com>
-allOf:
- - $ref: /schemas/pci/pci-host-bridge.yaml#
-
properties:
compatible:
enum:
@@ -21,18 +18,12 @@ properties:
- xlnx,versal-cpm5nc-host
reg:
- items:
- - description: CPM system level control and status registers.
- - description: Configuration space region and bridge registers.
- - description: CPM5 control and status registers.
- minItems: 2
+ minItems: 3
+ maxItems: 4
reg-names:
- items:
- - const: cpm_slcr
- - const: cfg
- - const: cpm_csr
- minItems: 2
+ minItems: 3
+ maxItems: 4
interrupts:
maxItems: 1
@@ -72,10 +63,53 @@ required:
- msi-map
- interrupt-controller
+allOf:
+ - $ref: /schemas/pci/pci-host-bridge.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,versal-cpm-host-1.00
+ then:
+ properties:
+ reg:
+ items:
+ - description: CPM system level control and status registers.
+ - description: Configuration space region and bridge registers.
+ - description: CPM clock and reset control registers.
+ reg-names:
+ items:
+ - const: cpm_slcr
+ - const: cfg
+ - const: cpm_crx
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,versal-cpm5-host
+ - xlnx,versal-cpm5-host1
+ then:
+ properties:
+ reg:
+ items:
+ - description: CPM system level control and status registers.
+ - description: Configuration space region and bridge registers.
+ - description: CPM5 control and status registers.
+ - description: CPM clock and reset control registers.
+ reg-names:
+ items:
+ - const: cpm_slcr
+ - const: cfg
+ - const: cpm_csr
+ - const: cpm_crx
+
unevaluatedProperties: false
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
versal {
#address-cells = <2>;
@@ -98,8 +132,10 @@ examples:
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
msi-map = <0x0 &its_gic 0x0 0x10000>;
reg = <0x0 0xfca10000 0x0 0x1000>,
- <0x6 0x00000000 0x0 0x10000000>;
- reg-names = "cpm_slcr", "cfg";
+ <0x6 0x00000000 0x0 0x10000000>,
+ <0x0 0xfca00000 0x0 10000>;
+ reg-names = "cpm_slcr", "cfg", "cpm_crx";
+ reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>;
pcie_intc_0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@@ -126,8 +162,10 @@ examples:
msi-map = <0x0 &its_gic 0x0 0x10000>;
reg = <0x00 0xfcdd0000 0x00 0x1000>,
<0x06 0x00000000 0x00 0x1000000>,
- <0x00 0xfce20000 0x00 0x1000000>;
- reg-names = "cpm_slcr", "cfg", "cpm_csr";
+ <0x00 0xfce20000 0x00 0x1000000>,
+ <0x00 0xfcdc0000 0x00 0x10000>;
+ reg-names = "cpm_slcr", "cfg", "cpm_csr", "cpm_crx";
+ reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>;
pcie_intc_1: interrupt-controller {
#address-cells = <0>;
--
2.44.1
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