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Message-ID: <qcvz3t55bu5zok5up5nxk3mxstzkcpmdavsm6t26pe5dwxyj2a@p6nkxe2fhvvv>
Date: Wed, 26 Mar 2025 19:41:57 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
Cc: Georgi Djakov <djakov@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>,
        Odelu Kukatla <quic_okukatla@...cinc.com>,
        Mike Tipton <quic_mdtipton@...cinc.com>,
        Jagadeesh Kona <quic_jkona@...cinc.com>,
        Jeff Johnson <jeff.johnson@....qualcomm.com>,
        Sibi Sankar <quic_sibis@...cinc.com>, linux-arm-msm@...r.kernel.org,
        linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH V10 6/7] arm64: dts: qcom: sa8775p: add EPSS l3
 interconnect provider

On Mon, Mar 24, 2025 at 06:32:02PM +0000, Raviteja Laggyshetty wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P
> SoCs. L3 instances on this SoC are same as SM8250 and SC7280 SoCs.
> These SoCs use EPSS_L3_PERF register instead of REG_L3_VOTE register for
> programming the perf level. This is taken care in the data associated
> with the target specific compatible. Since, the HW is same in the all
> SoCs with EPSS support, using the same generic compatible for all.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>

-- 
With best wishes
Dmitry

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