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Message-ID: <87h63exvlt.ffs@tglx>
Date: Thu, 27 Mar 2025 17:54:22 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Sean Christopherson <seanjc@...gle.com>
Cc: Neeraj Upadhyay <Neeraj.Upadhyay@....com>, linux-kernel@...r.kernel.org,
 bp@...en8.de, mingo@...hat.com, dave.hansen@...ux.intel.com,
 Thomas.Lendacky@....com, nikunj@....com, Santosh.Shukla@....com,
 Vasant.Hegde@....com, Suravee.Suthikulpanit@....com, David.Kaplan@....com,
 x86@...nel.org, hpa@...or.com, peterz@...radead.org, pbonzini@...hat.com,
 kvm@...r.kernel.org, kirill.shutemov@...ux.intel.com, huibo.wang@....com,
 naveen.rao@....com
Subject: Re: [RFC v2 13/17] x86/apic: Handle EOI writes for SAVIC guests

On Thu, Mar 27 2025 at 07:19, Sean Christopherson wrote:
> On Thu, Mar 27, 2025, Thomas Gleixner wrote:
>> Actually no. As this is for 8 byte alignment. For 16 byte it's 
>> 
>> 	bit = vector + 96 * (vector / 32);
>> ergo
>>         vector = bit - 24 * (bit / 32);
>> 
>> Which is still just shifts and add/sub.
>
> IIUC, the suggestion is to use find_last_bit() to walk the entire 128-byte range
> covered by ISR registers, under the assumption that the holes are guaranteed to
> be zero.  I suppose that works for Secure AVIC, but I don't want to do that for
> KVM since KVM can't guarantee the holes are zero (userspace can stuff APIC state).

Fair enough. So yes, then making the current KVM function generic is the
right thing to do.

Thanks,

        tglx

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