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Message-ID: <20250328-wise-chocolate-marten-bdccd6@krzk-bin>
Date: Fri, 28 Mar 2025 09:09:00 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Jagadeesh Kona <quic_jkona@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Konrad Dybcio <konradybcio@...nel.org>, Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>, 
	Dmitry Baryshkov <lumag@...nel.org>, Ajit Pandey <quic_ajipan@...cinc.com>, 
	Imran Shaik <quic_imrashai@...cinc.com>, Taniya Das <quic_tdas@...cinc.com>, 
	Satya Priya Kakitapalli <quic_skakitap@...cinc.com>, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Subject: Re: [PATCH v3 01/18] dt-bindings: clock: qcom,sm8450-videocc: Add
 MXC power domain

On Thu, Mar 27, 2025 at 03:22:21PM +0530, Jagadeesh Kona wrote:
> To configure the video PLLs and enable the video GDSCs on SM8450,
> SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along

Either your patches are not ordered correctly or you forgot that
SC8280xp also gets MXC.

Best regards,
Krzysztof


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